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91results about How to "Reduce synchronization overhead" patented technology

Distributed type dynamic cache expanding method and system supporting load balancing

The invention discloses a distributed type dynamic cache expanding method and system supporting load balancing, which belong to the technical field of software. The method comprises steps of: 1) monitoring respective resource utilization rate at regular intervals by each cache server; 2) calculating respective weighing load value Li according to the current monitored resource utilization rate, and sending the weighting load value Li to a cache clustering manager by each cache server; 3) calculating current average load value of a distributed cache system by the cache clustering manager according to the weighting load value Li, and executing expansion operation when the current average load value is higher than a threshold thremax; and executing shrink operation when the current average load value is lower than a set threshold thremin. The system comprises the cache servers, a cache client side and the cache clustering manager, wherein the cache servers are connected with the cache client side and the cache clustering manager through the network. The invention ensures the uniform distribution of the network flow among the cache nodes, optimizes the utilization rate of system resources, and solves the problems of ensuring data consistency and continuous availability of services.
Owner:济南君安泰投资集团有限公司

Cluster packet synchronization optimization method and system for distributed deep neutral network

The invention discloses a cluster packet synchronization optimization method and system for a distributed deep neutral network. The method comprises the following steps of grouping nodes in a cluster according to the performance, allocating training data according to the node performance, utilizing a synchronous parallel mechanism in the same group, using an asynchronous parallel mechanism between the different groups and using different learning rates between the different groups. The nodes with the similar performance are divided into one group, so that the synchronization overhead can be reduced; more training data can be allocated to the nodes with the good performance, so that the resource utilization rate can be improved; the synchronous parallel mechanism is used in the groups with the small synchronization overhead, so that an advantage of good convergence effect of the synchronous parallel mechanism can be exerted; the asynchronous parallel mechanism is used between the groups with the large synchronization overhead, so that the synchronization overhead can be avoided; the different groups uses the different learning rates to facilitate model convergence. According to the method and the system, a packet synchronization method is used for a parameter synchronization process of the distributed deep neutral network in a heterogeneous cluster, so that the model convergence rate is greatly increased.
Owner:HUAZHONG UNIV OF SCI & TECH

Low-energy consumption sleeping monitoring method synchronous relative to time of wireless sensor network

The invention relates to a low-energy consumption sleeping monitoring method synchronous relative to time of a wireless sensor network. The traditional method is high in energy consumption. The method in the invention comprises the following steps: in the stage of creating a relative synchronization table at a new node, broadcasting addition request network packets by the new node firstly to obtain synchronizing information of a neighbourhood node; then estimating clock skew, and linearly fitting multigroup of synchronization information of the neighbourhood node to estimate clock drift; and finally saving the sleeping period of the neighbourhood node, the estimated clock skew and the clock drift into the relative synchronization table; and in the stage of prediction and transmission of data packets of the node, realizing relative synchronization with a target node by the node according to the created relative synchronization table, then predicting the waking time at the next time according to the sleeping period of the node, setting a transmission timer, and finally transmitting data packets by a short permeable when the transmission timer is triggered. According to the invention, the energy overhead for sending the data packets by the node can be saved, and the idle time of a transmitting node is reduced, and the sleeping time of the transmitting node is increased.
Owner:HANGZHOU DIANZI UNIV

Video decoding macro-block-grade parallel scheduling method for perceiving calculation complexity

The invention discloses a video decoding macro-block-grade parallel scheduling method for perceiving calculation complexity. The method comprises two critical technologies: the first one involves establishing a macro-block decoding complexity prediction linear model according to entropy decoding and macro-block information after reordering such as the number of non-zero coefficients, macro-block interframe predictive coding types, motion vectors and the like, performing complexity analysis on each module, and fully utilizing known macro-block information so as to improve the parallel efficiency; and the second one involves combining macro-block decoding complexity with calculation parallel under the condition that macro-block decoding dependence is satisfied, performing packet parallel execution on macro-blocks according to an ordering result, dynamically determining the packet size according to the calculation capability of a GPU, and dynamically determining the packet number according to the number of macro-blocks which are currently parallel so that the emission frequency of core functions is also controlled while full utilization of the GPU is guaranteed and high-efficiency parallel is realized. Besides, parallel cooperative operation of a CPU and the GPU is realized by use of a buffer area mode, resources are fully utilized, and idle waiting is reduced.
Owner:HUAZHONG UNIV OF SCI & TECH

Beidou/global position system (GPS) time signal-based time service system for communication network

The invention discloses a Beidou/global position system (GPS) time signal-based time service system for a communication network. The system comprises a power module 1, a Beidou module 2, a GPS module 3, a clock module 4, a master control module 5 and a panel module 6, which are combined into a whole. Beidou/GPS time is used for synchronizing the clock of a constant temperature crystal, the accuracy and stability of the clock frequency of the crystal are improved, high-accuracy and high-stability radio station time service signals and standard time service signals are output through the clock, and an external time service signal input interface is provided. A precision phase difference compensation technology and a time service error control technology are adopted, so that the synchronization time of a frequency hopping radio station is shortened, synchronization hold-in and synchronization maintenance during a radio silence period are ensured, and the synchronization overhead of the radio station is reduced. High-accuracy RS232-level and RS422-level standard time service signals are provided, so that the requirements of modern communication for the high accuracy of time signals can be met. The system has the characteristics of rational design, high reliability, high environmental adaptability, small size, convenience for use and the like.
Owner:武汉中元通信股份有限公司

Wireless sensor network routing method with high robustness and low delay

ActiveCN106851766AShort average end-to-end latencyGood data transfer efficiencyNetwork topologiesData needsMobile wireless sensor network
The invention provides a wireless sensor network routing method with high robustness and low delay. The wireless sensor network routing method comprises several stages of network initialization, period detection, path discovery and data forwarding, and comprises the following steps: sending an initialization packet by a base station, receiving the initialization packet by a node, establishing a neighbor node set, and periodically broadcasting a detection packet; replying a detection ACK packet by the node after waiting for a random time; updating the neighbor node set; and when data need to be sent, starting the path discovery, finding a fast path leading to a destination node, making response by the destination node after receiving the detection, determining assistance nodes on the way of the path, finally returning acknowledgement to a source node, sending the data by the source node according to a detection result, making decision by each node on the way according to the detected information and delay information, and finally sending the data to the destination node. According to the method, the average end-to-end delay is shortened by the reliable path discovery, the robustness is improved on the basis of ensuring the delay by using all kinds of fault-tolerant mechanisms, and no synchronization is required, therefore the synchronization cost is reduced.
Owner:NORTHWEST UNIV

Simultaneous frame and bit combined estimation method for EBPSK (extended binary phase shift keying) communication system

The invention discloses a simultaneous frame and bit combined estimation method for an EBPSK (extended binary phase shift keying) communication system. The method comprises the steps: framing sending data at a transmitting end, and then performing EBPSK modulation; sending a receiving signal into an impact filter at a receiving end, and converting the receiving signal into parasitic amplitude modulation impact at a code element '1'; performing down sampling on output data of the impact filter according to a relative relation with a baseband code element rate; calculating peak values of 13 continuous data points of each group in a data stream subjected to down sampling, marking the moment that the peak values are greater than a certain threshold value, calculating a relevance value to a frame header, and marking the moment, in which four times of the peak value is smaller than the relevance value, in the marked moments; searching the first peak value of the relevance value in the marked moment in the step, wherein the moment corresponding to the first peak value is a synchronous moment. According to the simultaneous frame and bit combined estimation method, frame and bit are simultaneously finished by one step, so that the synchronization efficiency is improved, the synchronization precision is improved, the demodulation performance is high, the synchronization expense is reduced, the transmission efficiency is high, the hardware expenses are reduced, and the receiving machine implementation cost is reduced.
Owner:苏州东奇信息科技股份有限公司

Method for executing dynamic allocation command on embedded heterogeneous multi-core

The invention discloses a method for executing a dynamic allocation command on embedded heterogeneous multi-core in the technical field of computers. The method comprises the following steps of: partitioning a binary code program to obtain a plurality of basic blocks; respectively selecting each basic block so as to obtain a target processing core for executing each basic block; translating a basic block which corresponds to the obtained target processing core so as to obtain a translated binary code on the target processing core; and performing statistics on execution frequency of each basicblock, marking a basic block of which the execution frequency is greater than a threshold value T as a hot-spot basic block, and caching the translated binary code of the hot-spot basic block into the cache. The method dynamically allocates commands onto each heterogeneous multi-core to be executed according to the processing capacity and load condition of the system multi-core and the like, so that the method overcomes the defect that static scheduling cannot dynamically allocate resources and also reduces the complexity of dynamic thread division. Therefore, the execution efficiency of the program on the heterogeneous multi-core is further improved.
Owner:SHANGHAI JIAO TONG UNIV

Multi-core processor synchronization method based on delay fence synchronization operation instruction

The invention discloses a multi-core processor synchronization method based on a delay fence synchronization operation instruction, and the method comprises the steps: enabling all participating coreprocessors to send out a synchronization arrival signal of the core processor at a synchronization arrival station, and confirming whether other core processors participating in the fence synchronization all arrive at a synchronization inspection station; and if yes, enabling the core processor to continue to execute, otherwise, enabling the core processor to enter a waiting state until the last arrived signal sent by the core processor is checked by the core processor. The synchronous arrival station is a pipeline station where the synchronous arrival station is located in a self-synchronousstate updating mode; the synchronous check station is a pipeline station where the synchronous state of other cores is inquired, and when the synchronous check station and the synchronous arrival station are not the same pipeline station, the non-adjacent synchronization mode is delay synchronization. The method has the advantages that the method is realized based on any instruction type, extra fence synchronization operation can be reduced, and the transaction synchronization efficiency is improved.
Owner:NAT UNIV OF DEFENSE TECH

GPU-based 5G multi-user LDPC code high-speed decoder and decoding method thereof

The invention provides a 5G multi-user LDPC code high-speed decoder based on a GPU and a decoding method thereof. The 5G multi-user LDPC code high-speed decoder comprises a high-speed decoder architecture and a high-speed decoding method. The decoding method comprises the following steps: 1, initializing a storage space of a host end; 2, initializing the GPU equipment; 3, carrying out LDPC basis matrix information structure weight description; 4, the host side dispatches GPU decoding; 5, copying LLR information; 6, distributing a corresponding thread number by the GPU end according to the user code block information, selecting a corresponding basis matrix information structural body, and performing iterative decoding based on a hierarchical minimum sum algorithm; 7, symbol judgment; and 8, returning the result to the host end. According to the method, the characteristics of a hierarchical decoding algorithm and the architecture characteristics of the GPU are fully combined, GPU on-chip resources are fully utilized, the memory access efficiency and the utilization rate of a data calculation unit are improved, the decoding time of a single code block is shortened while the resource consumption of the single code block is reduced, and the overall information throughput is improved; the decoding mode is more suitable for processing multi-cell and multi-user LDPC code block decoding in an actual scene.
Owner:BEIHANG UNIV
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