A demodulator (101) comprises a sampling stage (112), a hold stage (114), and a final stage (116). The sampling stage (112) includes at least one mixer (132) designed to be controlled by complementary
clock signals synchronously with a carrier frequency of an input
signal (122) in order to demodulate the input
signal (122) and generate a sampled
signal (126). The hold stage (114) includes at least a first
capacitor circuit (134A) designed to output the sampled signal (126) as a first hold signal (128A) after delaying the sampled signal (126), and a second
capacitor circuit (134B) designed to output the sampled signal (126) as a second hold signal (128B) after delaying the sampled signal (126). The final stage (116) is designed to alternately couple the first hold signal (128A) and the second hold signal (128B) as a demodulated output signal (124).