4 results about "Sampling clock offset" patented technology

This application provides a reference signal sending method and receiving method and an apparatus. A terminal device generates a frame. The frame includes data and a plurality of reference signals, and a difference between start positions of two adjacent reference signals is associated with a maximum sampling clock offset allowed by the terminal device. According to the method, a performance loss caused by a sampling clock offset introduced by a low-precision ring oscillator can be reduced, and receiving performance of a receiving device can be improved.

The invention relates to a signal equalization method and device based on sampling clock skew and a medium, and the method comprises the specific steps: introducing sampling clock skew to a received signal sequence at a receiving end, and obtaining a processed signal sequence; performing cross-correlation operation on the processing signal sequence and the sending signal sequence to obtain a cross-correlation sequence; obtaining a cross-correlation value of a specific interval according to the cross-correlation sequence, and obtaining an equilibrium vector; performing Fourier transform, reciprocal operation and inverse Fourier transform on the equalization vector to obtain an equalizer; and inputting the received signal sequence into an equalizer to obtain an equalized signal sequence. Compared with the prior art, the method has the advantages of simplicity in implementation, high flexibility, easiness in integration and the like.

A reference signal sending method and receiving method and a related apparatus are disclosed. A terminal device generates a frame including data and a plurality of reference signals. The frame is arranged such that a difference between start positions of two adjacent reference signals is associated with a maximum sampling clock offset allowed by the terminal device. According to the method, the performance loss caused by a sampling clock offset introduced by the low-precision ring oscillator can be reduced, and receiving performance of a receiving device can be improved.

The application relates to the technical field of signal processing, and relates to a sampling clock deviation and channel joint estimation method, equipment and intelligent fusion terminal under a power line scene. The sampling clock deviation and channel joint estimation method under the power line scene comprises the following steps: acquiring a continuous-time receiving signal; sampling the continuous-time receiving signal to obtain a time-domain receiving signal sampling sequence; performing discrete Fourier transform on each time-domain receiving signal sampling point in the time-domain receiving signal sampling sequence to obtain a frequency-domain receiving signal sequence; selecting two adjacent frequency-domain receiving signals in the frequency-domain receiving signal sequence; calculating an estimated value of the sampling clock deviation and an estimated value of a time-domain channel response according to a closed expression; performing discrete Fourier transform on the estimated value of the time-domain channel response to obtain an estimated value of a frequency-domain channel response, so that a sampling clock deviation and channel joint estimation result is obtained; and the application can reduce the calculation complexity of the sampling clock deviation and channel joint estimation.