53 results about "Signaling nodes" patented technology

In response to a programmatic request, configuration information representing a multi-network-segment gateway established on behalf of a customer is stored at a networking service. In response to another programmatic request, a communication session is established between a route signaling node of the gateway and a routing information source located at a customer premise. In response to additional programmatic input, the networking service stores an indication that the gateway is to be used to transfer packets between a cloud-side virtual network and a customer-side virtual network. The routing information exchanged in the session pertains to the cloud-side and customer-side virtual network, and is used to transfer data packets between the two virtual networks.

The invention relates to the technical field of industrial automation and machine vision, in particular to a peripheral signal control method for a visual detection system, and the method comprises the steps: creating a virtual signal node for each peripheral in an upper computer, and configuring a time sequence parameter for a device function node; dragging the link nodes through a graphical interface to form an executable signal sequence triggered by a product in-place signal; in response to an initial event, the signal control unit records the position P0 of the reference encoder, and plans and generates an absolute execution position point of a complete sequence control instruction at one time so as to trigger a peripheral action; and the upper computer graphically monitors the node state and records a sequence log, and supports triggering of a standby sequence and pose offset self-adaptive compensation based on image feedback in case of abnormality. The system is suitable for quality detection of industrial products such as glass bottle mouths, solves the high-precision synchronization problem of multi-equipment cooperative control, and improves the reliability, detection precision and deployment flexibility of a visual detection system.

The invention relates to the technical field, in particular to an unmanned inspection method and system for a switch cabinet, and the method comprises the following steps: building an incidence relation between signal nodes through a graph neural network, improving the time sequence consistency of multi-source signals, enabling instrument reading and temperature and humidity signals to form a hierarchical structure under a unified time frame, and improving the accuracy of inspection. The logic association of state layering is enhanced, continuous sampling sequence features are extracted through a long-short-term memory network, the response sensitivity and time prediction capability to abnormal signal abrupt change are improved, amplitude matching of temperature difference and current signals is achieved under the same time index, early abnormal nodes are accurately recognized, and a dynamic positioning sequence is established. Through joint tradeoff of distance and energy consumption, path lengthens and energy peak values are reduced, task throughput and equipment availability are improved, timing sequence capture and trend judgment capabilities are enhanced in an anomaly recognition layer, and accuracy and continuity of inspection decision and reliability of safety assessment are integrally improved.

A high performance (HP) standard cell architecture for logic cells used in a semiconductor device or product. An example semiconductor device includes a plurality of cells surrounded by a cell boundary, and a backside power delivery network (PDN) routed to the plurality of cells. At least one cell of the plurality of cells has an arrangement of transistors within the cell boundary, the arrangement of transistors coupled together to generate an output signal at an output signal node. There is a metal 0 layer above the arrangement of transistors, the metal 0 layer includes one or more input signal traces and an output signal trace. The output signal trace and the input signal traces are substantially parallel inside the cell boundary and have a first width near the cell boundary; the output signal trace has a region of a wider metal 0 inside the cell boundary.

The invention discloses a chip IP interface information automatic analysis and connection modeling method, and relates to the technical field of integrated circuit verification, and the method comprises the steps: multi-source interface information collection: docking a design server through an FTP / SFTP protocol, automatically retrieving and capturing a target file, carrying out format preprocessing, and storing the collected original information through a database; heterogeneous information fusion analysis: extracting port physical attributes and generating machine executable rules by constructing a grammar analyzer and a semantic analyzer respectively, and automatically judging multi-source information contradictions by adopting a three-level judgment mechanism; structuring modeling of the connection relation: constructing a directed graph model of the IP nodes, the signal nodes and the constraint nodes, and automatically executing directed graph model verification; and through a standardized API interface docking verification tool, outputting a model file and a report file in standardized JSON-LD and DOT formats. Through cooperative work of cross-format acquisition, double-engine analysis, structured modeling and standardized output, full-automatic processing of IP interface information is realized.

The invention provides a finite-state machine extraction method and device for logic system design and a storage medium, and the method comprises the steps: determining a signal node based on a condition trigger signal and an assignment signal of a process block in a compiling partition, so as to construct a first finite-state machine tree; associating a condition assignment statement for assigning the condition trigger signal to the corresponding signal node in the first finite-state machine tree to obtain a second finite-state machine tree; determining a signal value of the signal node based on a conditional statement corresponding to the conditional trigger signal and the conditional assignment statement, and updating the second finite-state machine tree based on the signal value to obtain a third finite-state machine tree; updating corresponding state transition information between the signal values of the signal nodes in the third finite-state machine tree to obtain a fourth finite-state machine tree; and combining the fourth finite-state machine trees to obtain a global finite-state machine result.

An overlay system is provided that includes a storage element and processing circuitry coupled thereto. The storage element stores an executable graph-based model having various signal nodes and connection links. The processing circuitry receives a stimulus and identifies a first signal node based on the stimulus. The processing circuitry determines a connection link coupled to the first signal node. The connection link includes an outward connection object defining association with the first signal node and an inward connection object defining association with a second signal node. The second signal node is thus identified based on the first connection link. The processing circuitry generates a signal using the first signal node and determines whether a signal potential of the signal exceeds a potential threshold associated with the first signal node. The processing circuitry, based on the signal potential exceeding the potential threshold, communicates the signal to the second signal node.

This application relates to the field of power distribution system technology, and in particular to a testing method and system for substation measurement and control devices based on neural networks. The method includes: constructing a full-link signal topology map of the substation; extracting the correlation features of each signal node from various types of configuration files; inputting the full-link signal topology map and correlation features into a pre-trained graph neural network, which matches signal node pairs to obtain matching point pairs, and generating a test sequence consisting of simulated excitation signals and expected response information based on the matching point pairs; triggering the corresponding simulated excitation signal according to the test sequence, acquiring feedback signals in real time, comparing the feedback signals with the expected response information, and determining the test results. This application effectively reduces the manual burden of testing substation measurement and control devices and improves test accuracy.

This invention relates to the field of adder circuit technology, specifically providing a 5-bit adder, an arithmetic operation circuit, a computing chip, and an electronic device. The adder consists of 40 transistors, including multiple XOR gates and inverters. The first input node of the third XOR gate is the first data input node, the second input node of the third XOR gate is the second data input node, the output node of the second inverter is the third data input node, the first input node of the first XOR gate is the fourth data input node, the second input node of the first XOR gate is the fifth data input node, the output node of the first inverter is the data output node, the output node of the third inverter is the first carry signal node, and the output node of the fifth inverter is the second carry signal node. This addresses the problem of the lack of high-efficiency, small-area, and high-speed 5-bit adders in related technologies.

This invention relates to the field of battery testing equipment and electrical connections, specifically to an integrated assembly of current, voltage, and temperature probe harnesses for cylindrical batteries. It comprises a probe holder, a rigid conductive busbar, a flexible sampling line, a probe, a tapered heat-shrink sleeve, and a phase-change thermoplastic elastomer. The assembly constructs an inverted V-shaped suspension cavity within the glue-filling cavity of the holder. The welding joint between the sampling line and the probe tail is wrapped by the heat-shrink sleeve and fitted within this suspension cavity, with the remaining gap filled with the phase-change elastomer. Its core principle is to utilize the Joule heat generated by the conductive busbar during testing to cause the elastomer to expand and rigidly lock into place. When subjected to external tension, the tapered heat-shrink sleeve wedges into the suspension cavity, generating a centripetal clamping force. This invention cleverly combines the flexibility and high rigidity of the materials, absorbing assembly stress at room temperature and effectively blocking the transmission of stress from mechanical vibrations to the signal nodes during operation, preventing microscopic loosening of the nodes due to reciprocating motion, and greatly improving connection reliability in complex environments.

A transceiver having a shared filter for both transmit and receive modes is disclosed. A transceiver includes a transmitter having an output coupled to a signal node, wherein the transmitter is configured to transmit signals onto the signal node during transceiver operation in a transmit mode. The transceiver also includes a receiver having an input coupled to the signal node, and configured to receive signals from the signal node during operation in the receive mode. The transceiver further includes a first filter coupled to the signal node, wherein the filter is shared by the transmitter and the receiver. The filter is coupled between the transceiver and a first terminal of a transmission line.

A delta-sigma analog-to-digital converter is provided that includes a continuous-time integration stage having an input terminal coupled through a switch to an input resistor that in turn couples to an input signal node. A feedback digital-to-analog converter converts a digital output signal to form a feedback current that also couples to the input terminal. A controller switches the first switch responsive to a duty cycle of the feedback current.

A phase interpolator for generating a phase interpolated output signal between two phase separated input signals received at two phase separated input signal nodes may include a plurality of circuit elements. The plurality of circuit elements may include at least one of resistors or capacitors, in a series arrangement between the two phase separated input signal nodes, where respective connection points between respective ones of the plurality of circuit elements may provide at least one intermediate phase interpolated signal. The phase interpolator may also include selection circuitry, which may be configured to select the phase interpolated output signal from the at least one intermediate phase interpolated signal.

The invention relates to the technical field of intelligent health management, in particular to a pelvic floor muscle training system based on a mobile terminal, which comprises a signal collaborative acquisition module, a multi-parameter linkage recognition module, a three-section action decomposition module, a time sequence voice guide module and an execution deviation evaluation module. According to the method, through synchronous time sequence analysis of pelvic floor electromyographic signals and heart rate signals in the training process, collaborative changes of signal mutation nodes are mined, multi-source physiological parameter linkage recognition and induction of action stage morphological characteristics are combined, training actions are disassembled into multi-stage processes, and time sequences of signal nodes and voice guidance are dynamically mapped; precise butt joint of step-by-step voice instructions and action states is achieved, performance of each stage of the training process is quantified into data features, training performance differences are visually evaluated through the time sequence deviation degree, scientificity and continuity of rehabilitation guidance are enhanced through a step-by-step feedback mechanism, and data basic support is provided for individual rehabilitation path adjustment and progress tracking.

The present disclosure provides a clock network optimization method, a computer device and a storage medium. The method comprises: obtaining a chip design layout, determining a signal node set and a receiving endpoint set according to the chip design layout; establishing a connection between the signal node set and the receiving endpoint set, generating an initial connection result; in response to the initial connection result not meeting a set target, adjusting the connection of the initial connection result, determining whether to accept the adjustment through a set strategy, generating an intermediate connection result; and in response to the intermediate connection result meeting the set target, determining the intermediate connection result as an optimization result.

Device comprising: a receive path for receiving, processing and outputting a receive radio frequency (RF) signal, wherein the receive path includes at least one low noise amplifier (LNA) and multiple signal nodes, and wherein the receive path is configurable to operate in multiple modes; at least one filter for filtering the receive RF signal;and at least one detector circuit to detect one or more levels occurring at one or more of the multiple signal nodes, wherein the device is configured to configure a sequence for the at least one LNA and the at least one filter, at least partially based on the one or more levels detected in the at least one detector circuit, wherein the device further comprises switching circuits connected to the receive path, wherein the switching circuits: in a first mode of the multiple modes are provided to cause the at least one detector circuit to detect the level of the received RF signal at an input of the at least one LNA via a first signal node of the multiple signal nodes;In a second mode of the several modes, the switching circuits are provided to cause the at least one detector circuit to detect the level of the received RF signal at an input of the at least one filter via a second signal node of the several signal nodes; and wherein in a third mode of the several modes, the switching circuits are provided to cause the at least one detector circuit to detect the level of the received RF signal at the input of the at least one LNA, wherein in the third mode the input of the at least one LNA is connected to an output of the at least one filter via a third signal node of the several signal nodes.

The invention provides a mobile storage device high-speed file transmission method and system based on multi-thread scheduling, and relates to the technical field of file transmission, and the method comprises the steps: setting an index authentication link of a mobile storage device during file transmission according to a scheduling relay node; performing sensitive identification on each transmission thread in multi-thread scheduling according to the index authentication link to obtain a throughput sensitive tag on each transmission thread, and further determining a parallel configuration signature when the file to be transmitted is transmitted in parallel among the transmission threads; and carrying out fragmentation marking on a transmission strategy of a to-be-transmitted file in the mobile storage device to obtain a message sending node strategy and a message receiving node strategy when the to-be-transmitted file is transmitted on the transmission thread, and carrying out cross-sequence transmission on the to-be-transmitted file in the mobile storage device through the resource verification path. According to the method and the device, strategy matching can be performed on the file transmission thread in a multi-thread scheduling environment between the mobile storage equipment and the target server, so that resource coordination in a file parallel transmission process is improved.

The invention provides a Q-value-variable bisecond-order filter based on resistance feedback, and belongs to the technical field of radio frequency receivers. Differential source followers are adopted to form a second-order filtering unit, a cross coupling resistance network is introduced between differential signal nodes, and a novel method for adjusting the quality factor of the filter is provided. The quality factor Q of the filter can be independently adjusted through an equivalent feedback path formed by the cross coupling resistor in a differential working state. In addition, a parasitic zero offset method is provided, negative capacitance is achieved by cross-coupling two capacitors between differential input and output nodes, and the stop-band suppression performance is improved. On the premise that the power consumption of the filter is not increased, the variable Q value and high linearity are realized, and the structure is suitable for a radio frequency receiver system and has a good engineering application prospect.

The invention discloses a transmitting device based on a DSP-DAC framework and a high-speed serial communication system, and relates to the field of serial communication, in the device, a digital processing unit processes a signal to be transmitted based on multi-tap FIR feedforward equalization to obtain B paths of parallel A-bit data signals; the low-speed data processing module obtains C paths of parallel A-bit data signals; the differential-pulse generation module under the ith group of DAC slices receives C paths of parallel ith-bit data signals so as to obtain C paths of parallel pulse signals, the merging and serializing driving module performs merging and serializing according to the C paths of parallel pulse signals, driving corresponding to the ith group of slice weight is performed through an SST driving structure so as to output a serialized differential signal corresponding to the ith bit, and the serial differential signal corresponds to the ith bit. And a target serialized differential signal is obtained through superposition. According to the scheme, parallel-to-serial processing and output driving are combined to set the merging-serializing driving module, and a full-rate signal node is only limited at a final output stage, so that the front-end circuit design is simplified, and high speed and completeness of an output signal are ensured.

An integrated circuit (100) includes a plurality of pins (104, 106, 108) including a signal output pin (108). The integrated circuit also includes a plurality of signal nodes (114N, 116N, 118N). Each of the plurality of signal nodes is operable to store a respective internal data signal. The integrated circuit also includes a plurality of test circuits (120, 122, 124). Each of the plurality of test circuits is configured to sample a respective internal data state and to couple a unique output signal to a same pin (104) of the plurality of pins other than the signal output pin in response to simultaneously coupling the unique output signal to the same pin.

The application discloses an interface generation system and method, a display terminal, a storage medium, an electronic device and a program product, relates to the technical field of host computer monitoring interface generation of a battery management system, and comprises the following steps: a file analysis module is used for extracting signal data and message data in a database container file; a metadata structure module generates parent nodes and associated child signal nodes with a message identifier as a unique identifier according to the signal data and the message data, and constructs a parent-child hierarchical data structure; a generation module establishes parent list controls and child list controls with a nested relationship according to the parent-child hierarchical data structure, and generates a display interface based on preset visual components bound to each signal attribute in the child list controls, so that the technical problem that the iterative updating process of the host computer monitoring interface for monitoring the battery state is complex and inefficient in the prior art is solved, the development efficiency is improved, and the manual consumption is reduced.

On-chip multi-band equalizers for adjusting signal strength for a receiver receiving multi-band frequency signals are provided. An example multi-band equalizer comprises multiple series connected tapped LC resonators. The tapped LC resonator may be capacitive tapping or inductive tapping, where both frequency and gain of the frequency bands of interest may be programmed by tuning the capacitances of the programmable capacitors and / or selecting the tapped-out terminals of the inductors. The multi-band equalizer may be connected to a signal node, for instance between two amplifiers in the receiver.

The invention relates to the technical field of vehicle controllers, in particular to a vehicle-mounted controller communication code generation method and device, equipment, a medium and a product, and the method comprises the steps: obtaining a communication definition file of a target vehicle and an identifier of a target vehicle-mounted controller; the communication definition file is screened based on the identification of the target vehicle-mounted controller, communication information of at least one communication signal in the target vehicle-mounted controller is extracted from the screened communication definition file, and the communication information comprises signal nodes and signal parameters; generating a corresponding interface signal and a signal buffer area interface definition according to the communication information of the at least one communication signal; judging the signal type of at least one communication signal based on the signal node, calling a corresponding communication code generation template based on the signal type, and filling the signal parameter, the interface signal and the signal buffer area interface definition into the communication code generation template; and writing the filled communication code generation template into an output file to generate a communication code of the target vehicle-mounted controller.

This invention discloses a method and system for suppressing distributed co-channel interference in a region-coexisting environment. The method includes: a desired signal node generating a desired signal and transmitting it through an antenna; distributed interference nodes generating interference signals and transmitting them through antennas; authorized receiving nodes receiving and processing the signals to obtain the down-converted received signal; converting the received distributed interference signal into real and imaginary parts, expanding it with respect to time error and residual frequency offset to obtain the interference signal expression after expansion with time error and residual frequency offset; merging the time-invariant coefficients before the real and imaginary parts of the interference signal into one term to obtain the reconstruction coefficient expression of the distributed interference; estimating the coefficients of the distributed interference suppression system model; reconstructing the interference signal; performing distributed interference suppression; and obtaining the desired signal. This invention achieves the reconstruction and suppression of distributed interference signals under constraints of time error, frequency offset, and IQ imbalance.

The embodiment of the application discloses a kind of based on function simulation architecture vulnerability factor calculation method and device, the method comprises: according to circuit design source file, circuit compilation is generated simulation data and circuit topology chart;According to test excitation and simulation data, function simulation is formed at each simulation time simulation result data;Simulation result data is backfilled into circuit topology chart, determines the visible input end information of each signal node in circuit under each simulation time;The visible input end information of each signal node under each simulation time is summarized and analyzed, determines the target time window that each signal node corresponding soft error can be observed;For each signal node, the proportion of its corresponding target time window in entire simulation period is calculated as the architecture vulnerability factor data of this signal node.The application greatly reduces the time overhead required for AVF data calculation, effectively improves the calculation efficiency of AVF data.

The utility model discloses a control signal networked transmission system, which relates to the field of medical control systems and comprises at least one control circuit, two microprocessors and at least one receiving circuit, the control circuit is electrically connected with one microprocessor, the receiving circuit is electrically connected with the other microprocessor, and the two microprocessors are electrically connected with the control circuit. The two microprocessors are connected through network transmission, the control circuit transmits a control signal received by one signal node to the receiving circuit through the two microprocessors, and the receiving circuit outputs the control signal to control the other signal node; according to the utility model, control signals of the signal nodes are transmitted in a networked manner, heavy cables are removed, space occupation is reduced, winding risks are avoided, stability of control signal transmission is ensured, installation cost is reduced, upgrading and reconstruction are convenient, rewiring is not needed when control nodes are increased, lightweight design of equipment is facilitated, wiring errors of the control signals are avoided, and reliability of the equipment is improved. And convenience and economic benefit guarantee are provided for transmission of control signals.

The application discloses a kind of LED street lamp multilevel networking control method and system based on Z-Wave gateway, it is related to wireless communication technical field, it introduces this role, and the link quality of its adjacent node is periodically detected by the role of signal node, maintains a real-time local link health table.When receiving the command of gateway, signal node first tries direct communication or selects the best neighbor node to perform relay forwarding using its local health table.If a local path fails due to sudden obstacles, the signal node does not need to report to the gateway, but can immediately retry according to the alternative path in the health table, intelligently bypassing the failure point.This combination of global routing macro guidance and local node autonomous decision-making effectively avoids transient communication interruptions caused by dynamic environmental changes, significantly improving the success rate of control commands in complex environments and system robustness.

The invention relates to the technical field of adder circuits, and particularly provides a 5-bit adder, an arithmetic operation circuit, a computing chip and electronic equipment, the adder is composed of 40 transistors and comprises a plurality of exclusive-OR gates and phase inverters, a first input node of a third exclusive-OR gate is a first data input node, and a second input node of a second exclusive-OR gate is a second data input node; a second input node of the third exclusive-OR gate is a second data input node, an output node of the second phase inverter is a third data input node, a first input node of the first exclusive-OR gate is a fourth data input node, a second input node of the first exclusive-OR gate is a fifth data input node, and an output node of the first phase inverter is a data output node; the output node of the third phase inverter is a first carry signal node, and the output node of the fifth phase inverter is a second carry signal node. The problem that a 5-bit adder which is high in energy efficiency, small in area and high in operation speed is lacked in the prior art is solved.

This application discloses a signaling node identification method, apparatus, device, storage medium, and computer program product. The method includes: for a first signaling node at any position in an actual signaling flow, determining the relative timing position of the first signaling node in the actual signaling flow; determining a basic position in a standard signaling flow corresponding to the actual signaling flow that matches the relative timing position; determining the reliability of each node type based on the node type of each second signaling node in the standard signaling flow and the relative position between each second signaling node and the basic position; and identifying the node type of the first signaling node based on the reliability of each node type, or based on the weighted reliability of each node type, wherein the weighted reliability is obtained by weighting the reliability. This application enables automatic identification of the node type for each first signaling node, allowing maintenance personnel to intuitively identify each node in the flow through the node type.

The invention relates to the technical field of integrated radio frequency, and particularly discloses a self-adaptive adjusting and testing frequency conversion module and a flatness traversal adjusting and testing method thereof.The self-adaptive adjusting and testing frequency conversion module comprises a signal transmission module used for transmitting radio frequency signals, an adjustable matching network module and a control module, and the signal transmission module is provided with a plurality of signal nodes electrically connected with the adjustable matching network module; the adjustable matching network module can independently regulate and control the capacitance value of each signal node; the control module is electrically connected with the signal transmission module and the adjustable matching network module, and is used for receiving the radio frequency signal output by the signal transmission module, comparing and analyzing flatness data of the radio frequency signal with preset target flatness data, and further controlling the adjustable matching network module to change capacitance values of the plurality of signal nodes. Therefore, the flatness of the signal output by the signal transmission module reaches the preset target. Signal node capacitance can be automatically regulated and controlled, the flatness of output signals reaches the standard, the problems of low efficiency and high cost of traditional debugging are solved, and the efficiency is improved and the cost is reduced.