Sampling clock?mismatch?background?correction method based on time-to-digital?converter

Abstract

The invention relates to a clock?correction technology in the field of microelectronics and discloses a sampling clock?mismatch?background?correction method based on a time-to-digital?converter, which is used for carrying out background?correction on mismatch of a sampling clock?of a time-interleaved analog-to-digital converter and improving performances of the time-interleaved analog-to-digital converter. AND operation is carried out on each adjacent two-phase sampling clock of the time-interleaved analog-to-digital converter, the overlapping part waveform Ai of the adjacent sampling clocks is obtained, a?time domain?waveform width?amplifier is adopted to amplify the width of Ai to obtain Ci, the time-to-digital?converter is used for quantifying Ci to obtain Di, the average value of Di D represents a digital code corresponding to the ideal overlapping width of adjacent two-phase sampling clocks, sampling clock offset in the i channel is obtained through calculation Ei=Di-D, and multiphase?sampling?clock?mismatch?correction can then be realized through Ei statistics and feeding the statistical result to a clock delay?adjustment unit. The sampling clock?mismatch?background?correction method based on time-to-digital?converter is particularly suitable for mismatch correction on the sampling clock of the time-interleaved analog-to-digital converter.

Description

technical field [0001] The invention relates to clock correction technology in the field of microelectronics, in particular to a sampling clock mismatch background correction method based on a time-to-digital converter. Background technique [0002] With the continuous improvement of integrated circuit manufacturing technology, high-speed, highly integrated digital circuits have been developed by leaps and bounds, and the digital signal processing capability has been continuously enhanced. In order to meet the demands of high-speed digital circuits, how to increase the speed of analog-to-digital converters has become the focus of attention of integrated circuit designers. [0003] An analog-to-digital conversion system that connects multiple analog-to-digital converters in parallel and uses interleaved clocks to make them work in turn has attracted widespread attention. Its characteristic is to improve the overall speed while maintaining each sub-ADC working at a lower freq...

AI Technical Summary

Problems solved by technology

However, in reality, there are non-ideal factors such as sampling time mismatch (Timing mismatch), gain mismatch (Gain mismatch), offset mismatch (Offset mismatch) and bandwidth mismatch (Bandwidth mismatch) among the sub-ADCs of each channel. , which seriously affects the dynamic performance of the entire ADC

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