38 results about "Instruction processing unit" patented technology

The embodiment of the invention provides a data processing device, a processor and a data processing method. The data processing apparatus includes an instruction distribution unit, an instruction information recording unit, an instruction processing unit, and a write-back control unit, the instruction distribution unit being configured to split a vector instruction into a plurality of microinstructions, and to distribute the plurality of microinstructions to the instruction processing unit; the instruction information recording unit is configured to record instruction state information corresponding to a plurality of microinstructions respectively; the instruction processing unit is configured to receive a plurality of micro-instructions, process each of the plurality of micro-instructions to obtain a corresponding execution result, and feed back a processing progress to the instruction information recording unit; and the write-back control unit is configured to select at least one to-be-written-back microinstruction from the instruction information recording unit to perform write-back operation based on the instruction state information, and the write-back operation is used for writing an execution result of the to-be-written-back microinstruction back to the register. The device can realize out-of-order write-back of the instruction and improve the execution efficiency of the instruction.

An electric vehicle charging master controller includes an instruction processing unit, a user interface module, and a charging interface module. Electric vehicle (EV) charging equipment is external to the controller. The instruction processing unit is configured to execute instructions for charging electric vehicles (EVs). The charging interface module is configured to receive information from the instruction processing unit and transmit information to the EV charging equipment. The instruction processing unit is configured to transmit information to the charging interface module, which is designed to cause the EV charging equipment to direct charging current to the plurality of EVs, one at a time. The instruction processing unit is also configured to transmit information to the charging interface module designed to cause the EV charging equipment to stop the charging current to each EV when a charging cessation criterion has been met.

A communication device includes a processing unit (PROC), a volatile memory (VMEM), a non-volatile storage medium (NMEM) having stored thereon a first set of instructions and a second set of instructions, and a communication unit (COMM) being coupled to the processing unit (PROC). During a transition from a standby mode of operation to an idle mode of operation, the first set of instructions is loaded into the volatile memory (VMEM) enabling the processing unit (PROC) to execute the loaded first set of instructions. During a transition from the idle mode of operation to an active mode of operation, the second set of instructions is additionally loaded into the volatile memory (VMEM) enabling the processing unit (PROC) to execute instructions from the loaded first set of instructions and the loaded second set of instructions. The processing unit is configured, in the idle mode of operation (PROC), to interact with the communication unit (COMM) for detecting, using instructions from the first set of instructions, whether a triggering message is received via the communication unit (COMM), and to initiate the transition from the idle mode of operation to the active mode of operation in response to the detection of the triggering message.

The application provides a remote control decoding device based on a Hamming code, comprising: a shift register, configured to convert acquired serial data based on a clock signal; two code table storage units, respectively configured to store preset Hamming code tables; a count comparison module, configured to intercept corresponding comparison bits based on the clock signal; and a comparator, configured to compare the comparison bits intercepted by the count comparison module with comparison bits corresponding to the serial data, and perform decoding based on preset decoding control logic in the case that a comparison result meets a preset condition, and send a decoding result to a preset instruction processing unit. The remote control decoding device based on the Hamming code does not need to occupy more hardware resources in the case that a code distance requirement is met, and has good universality and expansibility.

The invention belongs to the technical field of ticket business safety access, and provides a ticket business safety access system and method based on terminal network self-adaption and communication channel matching, and the main scheme is as follows: when a ticket buying terminal obtains a query instruction or a ticket buying instruction, the ticket buying terminal sends the query instruction or the ticket buying instruction to a first intermediate server; the first intermediate server performs communication channel matching when receiving a query instruction or a ticket buying instruction, sends the query instruction or the ticket buying instruction to the instruction processing unit behind the communication channel through the matched communication channel, and processes the query instruction or the ticket buying instruction through the instruction processing unit; whether the processed query instruction or ticket buying instruction is forwarded to a ticket service server is judged according to the processing result; and the ticket service server receives the query instruction or the ticket buying instruction processed by the first intermediate server, generates ticket service information in response to the query instruction or the ticket buying instruction, and forwards the ticket service information to the corresponding ticket buying terminal through the first intermediate server or directly sends the ticket service information to the corresponding ticket buying terminal.

Disclosed are an operandless instruction system-based processor and a computer including same. The operandless instruction system-based processor comprises: an instruction processing unit for processing instructions of a program, wherein the instructions are composed of operandless instructions without operands besides instructions for transmitting and receiving data; one or more function processing units for performing a plurality of functions for data processing; and a stack register for separating instruction processing by the instruction processing unit and data processing by the function processing units. Accordingly, the number of logic gates may be minimized and high efficiency may be maintained by using a simple instruction set that does not include operands.

The invention discloses a processor, a chip product, computer equipment and a data acquisition method, and relates to the technical field of chips. The processor comprises an instruction issuing unit used for splitting a batch instruction into n sub-instructions and issuing the n sub-instructions to an instruction processing unit in sequence, and n is a positive integer larger than 1; and the instruction processing unit is used for multiplexing the instruction related data corresponding to the first sub-instruction into instruction related data corresponding to the second sub-instruction aiming at the second sub-instruction in the n sub-instructions under the condition that the multiplexing mark corresponding to the second sub-instruction is the first mark so as to process the second sub-instruction according to the instruction related data corresponding to the first sub-instruction, the first sub-instruction and the second sub-instruction are adjacent instructions in the n sub-instructions; wherein the first mark is used for indicating that the instruction related data corresponding to the second sub-instruction and the instruction related data corresponding to the first sub-instruction are located in the same register, so that the number of requests for the register is reduced.

The invention provides a computing unit, an instruction fetching request processing method, electronic equipment and a medium. The computing unit comprises an instruction cache unit; the first instruction processing unit is used for generating a first instruction fetching request when a first instruction fetching condition is met, and the first instruction fetching request points to a thread beam-level instruction needing to be acquired; the second instruction processing unit is used for executing work group level instructions, and each work group level instruction comprises a plurality of thread beam level instructions; the instruction fetching request processing unit is used for generating a second instruction fetching request when a second instruction fetching condition is met, the second instruction fetching request points to a working group-level instruction needing to be acquired, arbitrating the first instruction fetching request and the second instruction fetching request according to a preset strategy, selecting one instruction fetching request from the first instruction fetching request and the second instruction fetching request and sending the selected instruction fetching request to the instruction caching unit; and sending the corresponding instruction data to the first instruction processing unit or the second instruction processing unit according to the source of the instruction fetching request. According to the invention, the fetch requests of the work group-level and thread beam-level instructions can be processed in parallel.

An intelligent electronic equipment base comprises a shell, the shell is internally provided with a communication module, and the communication module is used for being in communication connection with electronic equipment and receiving a first instruction sent by the electronic equipment to the communication module; the processing unit is electrically connected with the communication module, the processing unit is used for receiving the first instruction, the processing unit is further in control connection with a driving module, the driving module is used for driving a driven module to act, the driven module further comprises a supporting piece, and the supporting piece is used for supporting electronic equipment; the processing unit is further used for controlling the driving module to work according to the first instruction. The orientation of the electronic equipment is adjusted through linkage of the driven module and the supporting piece. The technical problem that the electronic equipment cannot adjust the orientation is solved.

Provided is an information processing device comprising: an instruction processing unit that inputs, to a language model, a first text which is an authenticity determination target and a second text which instructs an authenticity determination to be performed, and that acquires an authenticity determination result output from the language model; and an evaluation unit that evaluates a hallucination detection performance of the language model on the basis of whether or not the authenticity determination result is correct.

A processing unit is described that receives an instruction to perform a first operation on a first layer of a neural network, block dependency data, and an instruction to perform a second operation on a second layer of the neural network. The processing unit performs the first operation, which includes dividing the first layer into a plurality of input blocks, and operating on the input blocks to generate a plurality of output blocks. The processing unit then performs the second operation after the first operation has generated a set number of output blocks defined by the block dependency data.

This invention provides an image character acquisition device and program that inputs document images, including non-standard documents, and outputs combinations of item names and item values ​​in an easy and appropriate manner. [Solution] The image character acquisition server 1 comprises a document image acquisition unit 11 that acquires document images of documents, an instruction processing unit 12 that inputs the document images acquired by the document image acquisition unit 11 and an item acquisition instruction statement that instructs the AI ​​to extract item names and item values ​​contained in the document images and then acquire combinations of item names and item values, an instruction result acquisition unit 13 that acquires combinations of item names and item values ​​contained in the document images output by the AI ​​as a result of processing by the instruction processing unit 12, and an item combination output unit 14 that outputs combinations of item names and item values ​​acquired by the instruction result acquisition unit 13.

The application provides a data processing system and a chip, and relates to the technical field of data processing. The system comprises a master control unit, an instruction processing unit and a data processing unit. The master control unit is used for issuing a data processing instruction to the instruction processing unit. The instruction processing unit is used for analyzing the data processing instruction to determine the operator type indicated by the data processing instruction, and in the case that the operator type is a non-matrix multiplication-addition operation type, converting the data processing instruction into a data processing micro-instruction of a matrix multiplication-addition operation dimension according to a mapping rule corresponding to the operator type, and writing the data processing micro-instruction into a micro-instruction queue. The data processing unit is used for executing a data processing operation of the matrix multiplication-addition operation dimension according to the data processing micro-instruction in the micro-instruction queue. The chip hardware complexity is effectively reduced, the resource utilization rate and the overall computing efficiency are improved while multiple operators are uniformly accelerated.

The application relates to the technical field of waste gas treatment, and discloses a waste gas treatment intelligent early warning system based on digital twinning, which comprises a model construction module, a monitoring module, a factor extraction module and the like. The model construction module constructs a dynamic risk model and a three-dimensional concentration field model based on waste gas components and equipment operation state data, and combines simulation optimization parameters; the monitoring module generates a prediction table containing a risk index and a regulation parameter; the factor extraction module identifies risk correlation variables; the evaluation module calculates a risk accumulation index; the adjustment module updates the prediction table accordingly; and the early warning execution module triggers an alarm. The system is also provided with an instruction processing unit to realize conflict detection and priority management. The system improves the risk early warning accuracy and the intelligent regulation level, is suitable for an industrial waste gas treatment scene, and guarantees the treatment efficiency and safety.

A branch instruction processing unit determines whether a branch has been taken in response to a predetermined branch instruction, detects a branch misprediction, and completes the predetermined branch instruction. A prediction TAGE table RAM stores a prediction TAGE table that is used in branch prediction for fetch. An updating TAGE table RAM stores an updating TAGE table in which information that is similar to information of the prediction TAGE table is registered. In a case where writing for updating is not being performed on the updating TAGE table, an updating determination circuit receives notification of completion information relating to a predetermined branch instruction, acquires information relating to the predetermined branch instruction from the updating TAGE table, and determines whether updating will be performed. In a case where it has been determined that updating will be performed, the updating determination circuit updates the prediction TAGE table and the updating TAGE table.

This embodiment provides a nonvolatile memory capable of high-speed compression, a memory system, and a control method for a nonvolatile memory. According to this embodiment, the nonvolatile memory includes a memory chip and an instruction processing unit. Upon receiving a first instruction for compression from a controller, the instruction processing unit stores data read from a first location on the memory chip in the memory, transmits validity determination information for determining whether the data is valid to the controller, and upon receiving a second instruction for compression and validity determination information specifying valid data from the controller, writes valid data from the data stored in the memory to a second location on the memory chip.

The application discloses an instruction processing device, method, processor and computer equipment, and belongs to the technical field of computers. The instruction processing device comprises an execution unit and a processing unit. The execution unit is used for executing a first instruction to obtain an execution result of the first instruction, and the first instruction is any instruction in candidate instructions. The processing unit is used for discarding the execution result of the first instruction in the case that the execution result of the first instruction meets a discard condition. The discard condition is used for indicating that other instructions in the candidate instructions except the first instruction are still normally executed after the execution result of the first instruction is discarded. Based on the above device, method, processor and computer equipment, the execution times of write operations can be reduced by discarding the execution result of the first instruction, so that the power consumption of the processor can be saved, and the performance of the processor can be improved.

The invention provides an artificial intelligence processor, an electronic device and an instruction processing method. The artificial intelligence processor comprises an instruction processing unit which is configured to sequentially acquire a plurality of instructions for processing; an instruction trajectory tracking apparatus includes an encoding module configured to: acquire a first time interval between a start processing time of a first instruction and a start processing time of a second instruction of a plurality of instructions, the second instruction immediately following the first instruction, determine the first time interval as an instruction delay of the second instruction, and encode the first instruction and the second instruction. The instruction delay is encoded in a first encoding format of the at least one variable length encoding format. The artificial intelligence processor can determine the execution track of the instruction of the program with relatively low memory and transmission cost so as to accurately and fully obtain the instruction delay.

To solve the problem in which it may be difficult to appropriately perform modifications or other processing on portions of text data output by a trained model.SOLUTION: A processing device has a segmentation processing unit that divides text data output by an LLM (Large Language Model) into one or more texts, and an instruction processing unit that executes processing corresponding to instructions on a text-by-text basis, on the basis of instructions for each text segmented by the segmentation processing unit.SELECTED DRAWING: Figure 9

The embodiment of the invention provides a processor, a chip, electronic equipment and an instruction processing method, and belongs to the technical field of chips. The processor comprises an instruction processing unit and a stack. The instruction processing unit is used for generating current instruction execution information and storing the current instruction execution information to the stack in the current instruction execution process; the current instruction execution information comprises address information of a next instruction to be executed, address information of a convergent point instruction and recursive depth information; the recursion depth information represents a difference value between the executed times of the function call instruction and the executed times of the return instruction; after the current instruction is executed, instruction execution information is read from the stack; and if it is determined that the next instruction address to be executed is the same as the convergent point instruction address and the difference value is 0, performing a stack-out operation on the stack, and returning to the operation of reading the instruction execution information from the stack until the stack is empty. According to the method and the device, the problem of calculation error of a thread program counter in a recursive function nesting scene can be avoided.

The application relates to the technical field of specific computing model data processing, and discloses an adaptive data modeling system based on an interactive graphical interface, which comprises an interactive instruction processing unit, a stability analysis unit, an operator evolution execution unit and a closed-loop feedback constraint unit; the stability analysis unit extracts stability characteristic quantities through a Hessian matrix of a bottom layer computing graph; the operator evolution execution unit simulates operator states according to a topological prediction disturbance sequence and performs adaptive reconstruction; and the closed-loop feedback constraint unit adjusts mapping weights in a logic mapping space according to the stability characteristic quantities, and maintains logic convergence by reducing an execution step length. The application maps the geometric characteristics of a bottom layer computing manifold into a negative feedback mechanism of an interactive space in real time, solves the problem of structural rigidity caused by mechanism transition of a dynamic system, and improves the precision of data modeling on the basis of guaranteeing the stability of model topological evolution.

The application belongs to the technical field of ticket security access, and proposes a ticket security access system and method based on terminal network self-adaptation and communication channel matching. The main scheme is as follows: when a ticket purchasing terminal obtains a query instruction or a ticket purchasing instruction, the terminal sends the instruction to a first intermediate server; the first intermediate server performs communication channel matching when receiving the query instruction or the ticket purchasing instruction, sends the instruction to an instruction processing unit after the communication channel through the matched communication channel, processes the query instruction or the ticket purchasing instruction through the instruction processing unit, and judges whether to forward the processed query instruction or the ticket purchasing instruction to a ticket server according to a processing result; the ticket server receives the query instruction or the ticket purchasing instruction processed by the first intermediate server, generates ticket information in response to the query instruction or the ticket purchasing instruction, and forwards the ticket information to a corresponding ticket purchasing terminal through the first intermediate server or directly sends the ticket information to the corresponding ticket purchasing terminal.

The light control command extension device includes an input interface, a processing unit, and an output interface. The input interface is configured to receive light control commands from a light control command source. The processing unit is configured to receive the light control commands and output extended light control commands. The light control commands correspond to a first number of light-emitting components, and the extended light control commands correspond to a second number of light-emitting components, wherein the first number is less than the second number. The output interface is configured to output the extended light control commands.

It is disclosed that to an operand-less instruction set architecture-based processor and a computer having the operand-less instruction set architecture-based processor. An operand-less instruction set architecture-based processor includes an instruction processing unit configured to process program instructions that do not require operands, except for instructions related to receiving and transmitting data; one or more functional processing units configured to perform a plurality of functions for data processing; and a stacked register configured to separate instruction processing by the instruction processing unit from data processing by the functional processing unit.

The invention discloses an intelligent incubator controller and system, and belongs to the technical field of intelligent control. The controller comprises a processing unit, a circuit control unit, a sensor and a network communication module. The processing unit obtains sensor data, interacts with a remote server through the network communication module, and receives a control instruction from a user mobile phone App; the processing unit generates a driving signal according to the instruction or a preset logic, and controls the circuit control unit to drive the execution mechanism, thereby achieving the precise regulation and control of the internal environment parameters of the incubator. The circuit control unit comprises a temperature adjusting unit, a humidity adjusting unit, an illumination adjusting unit and the like. The invention further comprises a control system composed of the controller, a remote server and a mobile terminal App. According to the invention, remote, intelligent and multi-parameter cooperative control and data tracing of an incubator environment are realized; and the system has the advantages of high intelligent degree, flexible control and wide protection range.

The present disclosure relates to a data processing method and device, as well as related products. The product includes a control module, which includes: an instruction cache unit, an instruction processing unit, and a storage queue unit; the instruction cache unit is used to store calculation instructions associated with the artificial neural network operation; the instruction processing unit is used to parse the calculation instructions to obtain multiple operation instructions; the storage queue unit is used to store an instruction queue, which includes: multiple operation instructions or calculation instructions to be executed in the order of the queue. Through the above method, the present disclosure can improve the operational efficiency of related products when performing neural network model operations.

The present disclosure relates to a data processing method and device, and related products. The product may include a control unit. The control unit may include an instruction caching unit, an instruction processing unit, and a storage queue unit. The instruction caching unit is configured to store a calculation instruction associated with an artificial neural network computation. The instruction processing unit may be configured to parse the calculation instruction to obtain a plurality of computation instructions. The storage queue unit may be configured to store an instruction queue, where the instruction queue may include a plurality of computation instructions or calculation instructions to be executed in a sequence of the queue. By adopting the above method, the present disclosure may improve a computation efficiency of the related products when performing a neural network model computation.

To provide a processor, an information processing device and a control method for a processor for reducing branch prediction latency.SOLUTION: A branch instruction processing unit determines whether a branch has occurred based on a given branch instruction, detects branch prediction errors, and completes the given branch instruction. A prediction TAGE table RAM 171 stores a prediction TAGE table used for branch prediction for fetching. An update TAGE table RAM 173 stores an update TAGE table, in which information similar to that in the prediction TAGE table is registered. An update determination circuit 172 determines whether to execute an update when it receives notification of the completion of a predetermined branch instruction and obtains information related to the predetermined branch instruction from the update TAGE table, provided that no write operation for updating has been performed on the update TAGE table. If it determines to execute the update, it updates both the prediction TAGE table and the update TAGE table.SELECTED DRAWING: Figure 3

The invention relates to a toy control system based on multi-modal interaction, which is integrated in a toy main body and comprises an instruction receiving unit for receiving a voice instruction through a microphone array; the instruction processing unit is used for carrying out localized recognition and semantic understanding on the voice instruction and generating a corresponding control instruction based on an action label output by a local semantic understanding model; and the action control unit is used for driving a motor to execute actions according to the control instruction and comprises advancing, retreating, head rotating or arm swinging of the toy main body. According to the control system, three interaction modes of voice, vision and action are fused, a localized edge computing framework is adopted, voice recognition response delay is controlled within 300 milliseconds, action and vision feedback are synchronously coordinated, time sequence dislocation is avoided, instant and accurate interaction is ensured, collaborative response of speaking, watching and moving at the same time is achieved, and the control system has the advantages of being simple in structure, convenient to operate and high in practicability. And the natural fluency of interaction and the use immersion of children are obviously improved.

The invention provides a data processing system and a chip, and relates to the technical field of data processing, the system comprises a main control unit, an instruction processing unit and a data processing unit; the main control unit is used for issuing a data processing instruction to the instruction processing unit; the instruction processing unit is used for analyzing the data processing instruction to determine an operator type indicated by the data processing instruction, and converting the data processing instruction into a data processing microinstruction of a matrix multiply-add operation dimension according to a mapping rule corresponding to the operator type under the condition that the operator type is a non-matrix multiply-add operation type; writing the data processing microinstruction into a microinstruction queue; and the data processing unit is used for executing data processing operation of a matrix multiplication and addition operation dimension according to the data processing microinstruction in the microinstruction queue. Unified acceleration of multiple operators is achieved, meanwhile, the chip hardware complexity is effectively reduced, and the resource utilization rate and the overall calculation efficiency are improved.