21 results about "Instruction processing unit" patented technology

The embodiment of the invention provides a data processing device, a processor and a data processing method. The data processing apparatus includes an instruction distribution unit, an instruction information recording unit, an instruction processing unit, and a write-back control unit, the instruction distribution unit being configured to split a vector instruction into a plurality of microinstructions, and to distribute the plurality of microinstructions to the instruction processing unit; the instruction information recording unit is configured to record instruction state information corresponding to a plurality of microinstructions respectively; the instruction processing unit is configured to receive a plurality of micro-instructions, process each of the plurality of micro-instructions to obtain a corresponding execution result, and feed back a processing progress to the instruction information recording unit; and the write-back control unit is configured to select at least one to-be-written-back microinstruction from the instruction information recording unit to perform write-back operation based on the instruction state information, and the write-back operation is used for writing an execution result of the to-be-written-back microinstruction back to the register. The device can realize out-of-order write-back of the instruction and improve the execution efficiency of the instruction.

A communication device includes a processing unit (PROC), a volatile memory (VMEM), a non-volatile storage medium (NMEM) having stored thereon a first set of instructions and a second set of instructions, and a communication unit (COMM) being coupled to the processing unit (PROC). During a transition from a standby mode of operation to an idle mode of operation, the first set of instructions is loaded into the volatile memory (VMEM) enabling the processing unit (PROC) to execute the loaded first set of instructions. During a transition from the idle mode of operation to an active mode of operation, the second set of instructions is additionally loaded into the volatile memory (VMEM) enabling the processing unit (PROC) to execute instructions from the loaded first set of instructions and the loaded second set of instructions. The processing unit is configured, in the idle mode of operation (PROC), to interact with the communication unit (COMM) for detecting, using instructions from the first set of instructions, whether a triggering message is received via the communication unit (COMM), and to initiate the transition from the idle mode of operation to the active mode of operation in response to the detection of the triggering message.

Disclosed are an operandless instruction system-based processor and a computer including same. The operandless instruction system-based processor comprises: an instruction processing unit for processing instructions of a program, wherein the instructions are composed of operandless instructions without operands besides instructions for transmitting and receiving data; one or more function processing units for performing a plurality of functions for data processing; and a stack register for separating instruction processing by the instruction processing unit and data processing by the function processing units. Accordingly, the number of logic gates may be minimized and high efficiency may be maintained by using a simple instruction set that does not include operands.

The invention discloses a processor, a chip product, computer equipment and a data acquisition method, and relates to the technical field of chips. The processor comprises an instruction issuing unit used for splitting a batch instruction into n sub-instructions and issuing the n sub-instructions to an instruction processing unit in sequence, and n is a positive integer larger than 1; and the instruction processing unit is used for multiplexing the instruction related data corresponding to the first sub-instruction into instruction related data corresponding to the second sub-instruction aiming at the second sub-instruction in the n sub-instructions under the condition that the multiplexing mark corresponding to the second sub-instruction is the first mark so as to process the second sub-instruction according to the instruction related data corresponding to the first sub-instruction, the first sub-instruction and the second sub-instruction are adjacent instructions in the n sub-instructions; wherein the first mark is used for indicating that the instruction related data corresponding to the second sub-instruction and the instruction related data corresponding to the first sub-instruction are located in the same register, so that the number of requests for the register is reduced.

The invention provides a computing unit, an instruction fetching request processing method, electronic equipment and a medium. The computing unit comprises an instruction cache unit; the first instruction processing unit is used for generating a first instruction fetching request when a first instruction fetching condition is met, and the first instruction fetching request points to a thread beam-level instruction needing to be acquired; the second instruction processing unit is used for executing work group level instructions, and each work group level instruction comprises a plurality of thread beam level instructions; the instruction fetching request processing unit is used for generating a second instruction fetching request when a second instruction fetching condition is met, the second instruction fetching request points to a working group-level instruction needing to be acquired, arbitrating the first instruction fetching request and the second instruction fetching request according to a preset strategy, selecting one instruction fetching request from the first instruction fetching request and the second instruction fetching request and sending the selected instruction fetching request to the instruction caching unit; and sending the corresponding instruction data to the first instruction processing unit or the second instruction processing unit according to the source of the instruction fetching request. According to the invention, the fetch requests of the work group-level and thread beam-level instructions can be processed in parallel.

An intelligent electronic equipment base comprises a shell, the shell is internally provided with a communication module, and the communication module is used for being in communication connection with electronic equipment and receiving a first instruction sent by the electronic equipment to the communication module; the processing unit is electrically connected with the communication module, the processing unit is used for receiving the first instruction, the processing unit is further in control connection with a driving module, the driving module is used for driving a driven module to act, the driven module further comprises a supporting piece, and the supporting piece is used for supporting electronic equipment; the processing unit is further used for controlling the driving module to work according to the first instruction. The orientation of the electronic equipment is adjusted through linkage of the driven module and the supporting piece. The technical problem that the electronic equipment cannot adjust the orientation is solved.

This invention provides an image character acquisition device and program that inputs document images, including non-standard documents, and outputs combinations of item names and item values ​​in an easy and appropriate manner. [Solution] The image character acquisition server 1 comprises a document image acquisition unit 11 that acquires document images of documents, an instruction processing unit 12 that inputs the document images acquired by the document image acquisition unit 11 and an item acquisition instruction statement that instructs the AI ​​to extract item names and item values ​​contained in the document images and then acquire combinations of item names and item values, an instruction result acquisition unit 13 that acquires combinations of item names and item values ​​contained in the document images output by the AI ​​as a result of processing by the instruction processing unit 12, and an item combination output unit 14 that outputs combinations of item names and item values ​​acquired by the instruction result acquisition unit 13.

The application provides a data processing system and a chip, and relates to the technical field of data processing. The system comprises a master control unit, an instruction processing unit and a data processing unit. The master control unit is used for issuing a data processing instruction to the instruction processing unit. The instruction processing unit is used for analyzing the data processing instruction to determine the operator type indicated by the data processing instruction, and in the case that the operator type is a non-matrix multiplication-addition operation type, converting the data processing instruction into a data processing micro-instruction of a matrix multiplication-addition operation dimension according to a mapping rule corresponding to the operator type, and writing the data processing micro-instruction into a micro-instruction queue. The data processing unit is used for executing a data processing operation of the matrix multiplication-addition operation dimension according to the data processing micro-instruction in the micro-instruction queue. The chip hardware complexity is effectively reduced, the resource utilization rate and the overall computing efficiency are improved while multiple operators are uniformly accelerated.

The application relates to the technical field of waste gas treatment, and discloses a waste gas treatment intelligent early warning system based on digital twinning, which comprises a model construction module, a monitoring module, a factor extraction module and the like. The model construction module constructs a dynamic risk model and a three-dimensional concentration field model based on waste gas components and equipment operation state data, and combines simulation optimization parameters; the monitoring module generates a prediction table containing a risk index and a regulation parameter; the factor extraction module identifies risk correlation variables; the evaluation module calculates a risk accumulation index; the adjustment module updates the prediction table accordingly; and the early warning execution module triggers an alarm. The system is also provided with an instruction processing unit to realize conflict detection and priority management. The system improves the risk early warning accuracy and the intelligent regulation level, is suitable for an industrial waste gas treatment scene, and guarantees the treatment efficiency and safety.

The application discloses an instruction processing device, method, processor and computer equipment, and belongs to the technical field of computers. The instruction processing device comprises an execution unit and a processing unit. The execution unit is used for executing a first instruction to obtain an execution result of the first instruction, and the first instruction is any instruction in candidate instructions. The processing unit is used for discarding the execution result of the first instruction in the case that the execution result of the first instruction meets a discard condition. The discard condition is used for indicating that other instructions in the candidate instructions except the first instruction are still normally executed after the execution result of the first instruction is discarded. Based on the above device, method, processor and computer equipment, the execution times of write operations can be reduced by discarding the execution result of the first instruction, so that the power consumption of the processor can be saved, and the performance of the processor can be improved.

The embodiment of the invention provides a processor, a chip, electronic equipment and an instruction processing method, and belongs to the technical field of chips. The processor comprises an instruction processing unit and a stack. The instruction processing unit is used for generating current instruction execution information and storing the current instruction execution information to the stack in the current instruction execution process; the current instruction execution information comprises address information of a next instruction to be executed, address information of a convergent point instruction and recursive depth information; the recursion depth information represents a difference value between the executed times of the function call instruction and the executed times of the return instruction; after the current instruction is executed, instruction execution information is read from the stack; and if it is determined that the next instruction address to be executed is the same as the convergent point instruction address and the difference value is 0, performing a stack-out operation on the stack, and returning to the operation of reading the instruction execution information from the stack until the stack is empty. According to the method and the device, the problem of calculation error of a thread program counter in a recursive function nesting scene can be avoided.

The application relates to the technical field of specific computing model data processing, and discloses an adaptive data modeling system based on an interactive graphical interface, which comprises an interactive instruction processing unit, a stability analysis unit, an operator evolution execution unit and a closed-loop feedback constraint unit; the stability analysis unit extracts stability characteristic quantities through a Hessian matrix of a bottom layer computing graph; the operator evolution execution unit simulates operator states according to a topological prediction disturbance sequence and performs adaptive reconstruction; and the closed-loop feedback constraint unit adjusts mapping weights in a logic mapping space according to the stability characteristic quantities, and maintains logic convergence by reducing an execution step length. The application maps the geometric characteristics of a bottom layer computing manifold into a negative feedback mechanism of an interactive space in real time, solves the problem of structural rigidity caused by mechanism transition of a dynamic system, and improves the precision of data modeling on the basis of guaranteeing the stability of model topological evolution.

The light control command extension device includes an input interface, a processing unit, and an output interface. The input interface is configured to receive light control commands from a light control command source. The processing unit is configured to receive the light control commands and output extended light control commands. The light control commands correspond to a first number of light-emitting components, and the extended light control commands correspond to a second number of light-emitting components, wherein the first number is less than the second number. The output interface is configured to output the extended light control commands.

It is disclosed that to an operand-less instruction set architecture-based processor and a computer having the operand-less instruction set architecture-based processor. An operand-less instruction set architecture-based processor includes an instruction processing unit configured to process program instructions that do not require operands, except for instructions related to receiving and transmitting data; one or more functional processing units configured to perform a plurality of functions for data processing; and a stacked register configured to separate instruction processing by the instruction processing unit from data processing by the functional processing unit.

The present disclosure relates to a data processing method and device, and related products. The product may include a control unit. The control unit may include an instruction caching unit, an instruction processing unit, and a storage queue unit. The instruction caching unit is configured to store a calculation instruction associated with an artificial neural network computation. The instruction processing unit may be configured to parse the calculation instruction to obtain a plurality of computation instructions. The storage queue unit may be configured to store an instruction queue, where the instruction queue may include a plurality of computation instructions or calculation instructions to be executed in a sequence of the queue. By adopting the above method, the present disclosure may improve a computation efficiency of the related products when performing a neural network model computation.

The invention provides a data processing system and a chip, and relates to the technical field of data processing, the system comprises a main control unit, an instruction processing unit and a data processing unit; the main control unit is used for issuing a data processing instruction to the instruction processing unit; the instruction processing unit is used for analyzing the data processing instruction to determine an operator type indicated by the data processing instruction, and converting the data processing instruction into a data processing microinstruction of a matrix multiply-add operation dimension according to a mapping rule corresponding to the operator type under the condition that the operator type is a non-matrix multiply-add operation type; writing the data processing microinstruction into a microinstruction queue; and the data processing unit is used for executing data processing operation of a matrix multiplication and addition operation dimension according to the data processing microinstruction in the microinstruction queue. Unified acceleration of multiple operators is achieved, meanwhile, the chip hardware complexity is effectively reduced, and the resource utilization rate and the overall calculation efficiency are improved.

A light-control instruction extension device is provided. The device includes an input interface, a processing unit, and an output interface. The input interface is configured to receive a light-control instruction from a light-control instruction source. The processing unit is configured to receive the light-control instruction and generate an extended light-control instruction. The light-control instruction corresponds to a first number of light-emitting elements, while the extended light-control instruction corresponds to a second number of light-emitting elements, wherein the second number is greater than the first number. The output interface is configured to output the extended light-control instruction, thereby enabling control of a larger number of light-emitting elements than natively supported by the light-control instruction source.

A processor, a graphics card, a computer device, and a dependency release method, relating to the field of chips. The processor is provided with a first-type pathway and a second-type pathway between an instruction processing unit and a dependency processing unit. The instruction processing unit is used for sending a first dependency release signal by means of the first-type pathway (222), and the dependency processing unit is used for releasing, on the basis of the first dependency release signal, an instruction dependency relationship corresponding to a first-type register (224); and the instruction processing unit is further used for sending a second dependency release signal by means of the second-type pathway (242), and the dependency processing unit is used for releasing, on the basis of the second dependency release signal, an instruction dependency relationship corresponding to a second-type register (244), wherein both the first-type register and the second-type register are registers used by a same instruction.

A light-control instruction extension device is provided. The device includes an input interface, a processing unit, and an output interface. The input interface is configured to receive a light-control instruction from a light-control instruction source. The processing unit is configured to receive the light-control instruction and generate an extended light-control instruction. The light-control instruction corresponds to a first number of light-emitting elements, while the extended light-control instruction corresponds to a second number of light-emitting elements, wherein the second number is greater than the first number. The output interface is configured to output the extended light-control instruction, thereby enabling control of a larger number of light-emitting elements than natively supported by the light-control instruction source.

The present disclosure provides an artificial intelligence processor, an electronic device, and an instruction processing method. The artificial intelligence processor comprises: an instruction processing unit, wherein the instruction processing unit is configured to sequentially obtain a plurality of instructions for processing; and an instruction trajectory tracking device comprising an encoding module, wherein the encoding module is configured to: obtain a first time interval between a start processing time of a first instruction and a start processing time of a second instruction in the plurality of instructions, wherein the second instruction is immediately after the first instruction, determine the first time interval as an instruction delay of the second instruction, and encode the instruction delay in a first encoding format in at least one variable length encoding format. The artificial intelligence processor can determine the execution trajectory of the instructions of the program with lower memory and transmission costs, and further accurately and sufficiently obtain the instruction delay.

Embodiments of this application provide example computing chips and instruction processing method related to the field of integrated circuit technologies. One example computing chip uses a superscalar processor architecture, and includes an instruction processing unit and a plurality of registers that are separately coupled to the instruction processing unit. The plurality of registers include a general purpose register and a plurality of private registers that are separately coupled to the general purpose register. The general purpose register is configured to store an execution result of a microinstruction that is in a plurality of microinstructions of a computing task and that is executed before a jump instruction and whose execution result is referenced by a microinstruction that is executed after the jump instruction. Each private register in the plurality of private registers is configured to store an execution result of any microinstruction in the plurality of microinstructions.