170 results about "Instruction processing unit" patented technology

A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.

A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.

The invention relates to a convolutional neural network hardware acceleration device, a convolution calculation method, and a storage medium. The device comprises an instruction processing unit, a hardware acceleration module and an external data memory unit, wherein the instruction processing unit decodes an instruction set to execute a corresponding operation so as to control the hardware acceleration module; the hardware acceleration module comprises an input caching unit, a data operation unit and an output caching unit, wherein the input caching unit executes the memory access operation of the instruction processing unit, and stores data read from the external data memory unit; the data operation unit executes the operation execution operation of the instruction processing unit, processes the data operation of the convolutional neural network, and controls a data operation process and a data flow direction according to an operation instruction set; the output caching unit executesthe memory access operation of the instruction processing unit, and stores a calculation result which is output by the data operation unit and needs to be written into the external data memory unit;and the external data memory unit stores a calculation result output by the output caching unit and transmits data to the input caching unit according to the reading of the input caching unit.

A method for operating a touch-control lock system according to a gesture or a figure, comprising steps of: (a) sensing a designated gesture or figure while a user uses his finger touches a touch-control panel of the touch-control lock system and outputting an electronic signal according to the designated gesture or figure; (b) processing the electronic signal by a micro-control unit and judging whether or not the electronic signal is a valid input by the micro-control unit; (c) determining whether or not the designated gesture or figure is valid by the micro-control unit; (d) loading correct data for the designated gesture or figure stored in a touch-control instruction processing unit and comparing the correct data with the designated gesture so as to determine if the designated gesture or figure is valid; and (e) outputting a control command to an application apparatus to react correspondingly.

The invention discloses an automatic lifting camera and a display device thereof. The camera device is arranged on the display device. The camera device comprises a camera assembly, an electromagnet assembly, a camera sliding assembly, an instruction processing unit, a control circuit, a lower device shell and an upper device shell. The instruction processing unit is used for acquiring a signal input by a user and outputting a control signal to the control circuit, and the control circuit is used for controlling on-off of an electromagnet of the electromagnet assembly according to the control signal. The electromagnet assembly is matched with a spring connected to the camera sliding assembly to control the camera sliding assembly to move along a sliding rail. The camera sliding assembly drives the camera assembly to move. The camera device automatically ascends to be used or descends to be hidden in the display device according to the user input signal, namely, the camera can be automatically retracted to the display device without manual operation, the using convenience is improved, and the sense of science and technology of the automatic lifting camera is enhanced.

A system that uses segmentation to safely execute native code. This system includes a processing element that executes the native code and a memory which stores code and data for the processing element. The processing element includes a segmentation mechanism which limits the native code executing on the processing element to accessing a specified segment of memory. The processing element also includes an instruction-processing unit, which is configured to execute a user-level instruction that causes the segmentation mechanism to limit memory accesses by the native code to the specified segment of the memory.

A system that uses segmentation to safely execute native code. This system includes a processing element that executes the native code and a memory which stores code and data for the processing element. The processing element includes a segmentation mechanism which limits the native code executing on the processing element to accessing a specified segment of memory. The processing element also includes an instruction-processing unit, which is configured to execute a user-level instruction that causes the segmentation mechanism to limit memory accesses by the native code to the specified segment of the memory.

A digital computer system capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their journey from a higher-level storage unit of the computer system to the functional units which process the instructions. The computer system includes an instruction compounding unit located intermediate to the higher-level storage unit and the cache storage unit for analyzing the instructions and generating for to each instruction a compounding information which indicates whether or not that instruction may be processed in parallel with one or more neighboring instructions in the instruction stream. These tagged instructions are then stored in the cache unit with the compounding information. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to these functional units are obtained from the cache storage unit. At instruction issue time, the compounding information for the instructions is examined and those instructions indicated for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.

The invention relates to a testing system of set-top box, which comprises input unit, operation command processor, remote-control signal sender, and detector. Wherein, the invention also provides a relative testing method which comprises that receiving the command at first format; converting said command into second format; using serial communication interface to send the signal at second format to the sender; the sender sends the remote-control signal to the set-top box to respond the signal at second format. The invention has high accuracy.

The invention provides a flight device control system. The flight device includes a first command processing unit used for converting control commands to driving signals controlling movement of a power unit of a flight device. The command processing unit includes a first command input system and a second command input system. The system also includes a console control system comprising a second command processing unit and a movement assembly. The second command processing unit is used for outputting commands for controlling the movement assembly to adjust the facing direction of a console camera and adjust the console camera in real time for keeping a to-be-shot body in a predetermined area of a shooting frame. The console camera can rotate in 360 degrees in the horizontal direction. According to the invention, complex flight device control commands are distributed to the first command input system and the second command input system reasonably and the second command system is set for manually inputting a part of flight device movement commands.

A microcontroller with an integrated special instruction processing unit and a programmable cycle state machine. The special instruction processing unit allows offloading of intensive processing of output data and the programmable cycle state machine minimizes the amount of customized, off chip circuitry necessary to connect the microcontroller to an external display.

A computer managing system includes an active system computer having a heart beat transmission processing unit for transmitting a heart beat signal indicating that an active system computer is being operated in normal to a spare system computer, and transmitting the heart beat signal to a first control unit; a spare system computer including a monitor request processing unit for transmitting a monitoring request of the active system computer to the first control unit in accordance with a determination result of whether or not a fault has occurred in the active system computer; and the first control unit including a heart beat transmit instruction processing unit for instructing a transmission of the heart beat signal to the first control unit, to the active system computer, when receiving the monitoring request from the spare system computer.

A computer managing system includes an active system computer having a heart beat transmission processing unit for transmitting a heart beat signal indicating that an active system computer is being operated in normal to a spare system computer, and transmitting the heart beat signal to a first control unit; a spare system computer including a monitor request processing unit for transmitting a monitoring request of the active system computer to the first control unit in accordance with a determination result of whether or not a fault has occurred in the active system computer; and the first control unit including a heart beat transmit instruction processing unit for instructing a transmission of the heart beat signal to the first control unit, to the active system computer, when receiving the monitoring request from the spare system computer.

A real-time processor includes a clock register updating a time at a predetermined interval, a time register storing an arbitrary time, a time comparator comparing the time in the clock register with the time stored in the time register, and an instruction processing unit executing an instruction whose execution status is altered according to the comparison result of the time comparator. A predetermined operation can be carried out correctly at a predetermined time since the instruction processing unit executes an instruction whose execution status is altered according to the comparison result of the time comparator.

The invention provides an information safety coprocessor for performing relevant operation by using a specific instruction set. The information safety coprocessor comprises a plurality of register files, an instruction processing unit, an operation unit, a direct memory access (DMA) engine, a local memory, a key memory and a context memory. The specific instruction set comprises a cryptographic algorithm execution instruction, a context operation instruction, a key access instruction, a data transmission instruction, a logical operation instruction and a register write instruction. Therefore, the information safety coprocessor has the advantages of function flexibility, low cost, high performance, multitask support and usability, and can meet complicated multifunction and multitask requirements with low cost.

A compiler of this invention generates an object program 20 in which an area allocation instruction 11 to allocate an area for a structure of a list vector to be accessed in a loop and an area deallocation instruction 12 are converted into a new area allocation instruction 21 and a new area deallocation instruction 22, respectively. A new area allocation instruction processing unit 31 called by the new area allocation instruction 21 allocates an area 51 allocated in one operation of a size which is not less than an integral multiple of the size of an area for a structure, clips an area from the area 51, and assigns the area to the structure on a first area allocation request. The new area allocation instruction processing unit 31 clips an area contiguous to that for a previous structure from the area 51 allocated in one operation and assigns the area to a structure on second and subsequent calls. A new area deallocation instruction processing unit 32 called by the new area deallocation instruction 22 deallocates the whole of the area 51 allocated in one operation when it becomes unnecessary.

A data processing apparatus and method are provided for executing a sequence of instructions including at least one multiple iteration instruction. The data processing apparatus comprises an instruction store for storing the sequence of instructions, and a processing unit for executing the sequence of instructions, the processing unit comprising at least a first processing path and a second processing path to enable at least two instructions of the sequence to be executed in parallel. When executing instructions in parallel, the first processing path executes an instruction which is earlier in the sequence than the instruction executing in the second processing path. The processing unit is operable when executing a multiple iteration instruction to allow a first iteration of the multiple iteration instruction to be executed in either the first processing path or the second processing path, but to cause all remaining iterations of the multiple iteration instruction to be executed in the first processing path. This provides a particularly efficient technique for executing the sequence of instructions.

The invention provides a voltage regulating device and an electronic device. The voltage regulating device comprises at least two voltage regulators and an instruction processing unit. The voltage regulators are used for supplying power to a load device. The instruction processing unit is coupled to the voltage regulators. A digital controller is coupled to the instruction processing unit through a two-way digital transmission interface, wherein the digital controller obtains state information of the voltage regulators through the instruction processing unit and correspondingly generates control instructions to the instruction processing unit according to the state information, and the instruction processing unit controls operation of the voltage regulators according to control instructions.

A processor device comprises: an instruction processing unit, which reads and successively executes a program on a memory device; an address register, which stores the absolute address of a pointer in the program; a range information register, which stores range information concerning the pointer by using the absolute address; and an exception generating unit, which, when the instruction processing unit accesses the memory device using the pointer concerning the address register, inputs the output of the instruction processing unit and the range information in the range information register and, if there is a range violation of the memory device, outputs an exception signal S1 to the instruction processing unit. A pointer and its access range information are associated in an inseparable manner and accurate access protection is performed even beyond a module.

According to the embodiments of the invention, a vehicle detection system and method are disclosed wherein the detection system comprises: acquiring devices, detection host computers, and a server. The acquiring devices, based on the detecting instruction sent from the detection host computer, obtain the detection data of a detected vehicle. The detection data obtained by the acquiring devices are used for damage evaluation by the server; and based on that, a detection report is generated. Since the instruction processing units in the acquiring devices are capable of processing and identifying the detecting instruction based on the actual condition of the detected vehicle, it is possible to carry out detection to the detected vehicle in a more targeted manner so as to cut the detection time and increase the detection efficiency. In addition, due to the plurality of acquiring devices and the plurality of detection host computers adopted by the system and method, the detection efficiency for second hand vehicles is further increased.

The invention discloses a broadcasting system with the emergency information issuing function, and belongs to the technical field of communication. The broadcasting system solves the problem that emergency information can not be issued anytime and anywhere through an existing broadcasting system. In one embodiment, the broadcasting system comprises a plurality of mobile terminals, an audio workstation, an addressable encoding controller, N telephone broadcast controllers, auxiliary TS encoders correspondingly connected with the telephone broadcast controllers, N short message broadcast controllers, auxiliary TS encoders correspondingly connected the short message broadcast controllers, a multiplexer, a demultiplexer, a plurality of broadcast receiving terminals and loudspeakers correspondingly connected with the broadcast receiving terminals, wherein each short message broadcast controller comprises a wireless communication module, a command processing unit, a storage module, a timing module, a text / audio conversion module and an authority management module. By the arrangement of the telephone broadcast controllers and the short message broadcast controllers, a worker can issue the emergency information anytime and anywhere in an emergency, and therefore the use flexibility of the broadcasting system is improved.

The invention discloses cooking equipment as well as an interaction device and method thereof. The interaction device comprises a touch display screen and a processing unit, wherein the touch display screen is used for providing an interactive interface so as to receive a touch instruction of a user through the interactive interface; the processing unit is connected with the touch display screen and is used for acquiring multiple working parameters of the cooking equipment according to the touch instruction, so that the cooking equipment is enabled to operate according to the multiple working parameters. Therefore, the multiple working parameters are put in the same interactive interface, the interactive interface is enabled to be more direct and clearer, setting of multiple parameters can be completed simultaneously through one-time operation, operating steps are simplified, the operating convenience is improved, and the user experience is improved.

The invention provides a flight device control system, which comprises a first instruction input system and a second instruction input system. The first instruction input system comprises a camera subsystem and an image processing subsystem. The camera subsystem is arranged on a flight device main body and is used for obtaining image and / or video information; the image processing subsystem is used for processing the image and / or video information to obtain position information of one or more main bodies in images and / or videos; and the image processing subsystem is connected with an instruction processing unit and is used for transmitting the position information, serving as an instruction, to the instruction processing unit. The flight device control system and control method combine two control modes, thereby simplifying control technique of a flight device, enhancing system shooting stability, and meanwhile, preventing the defect that an existing full-automatic following control mode is monotonous and unattractive, providing more interest for flight shooting and meeting special functions, such as self-shooting of an operator.

The invention discloses a microprocessor order split device based on implicit relevance and an implicit bypass, comprising a detecting and splitting unit required to split order, which is used for judging whether the coded order entering the microprocessor order split device is the order required to split and splitting the order required to split into two atom orders; a split order processing unit, which is used for receiving at least two atom orders split from the order required to split by the split unit required to split order, structuring the implicit relevance for these atom orders and outputting the processed atom order; the other processing unit, which is used for receiving the order judged to not require to split by the detecting and processing unit of the order required to split and the atom order finally generated by the split order processing unit, finishing the order subsequent process and executing work. When the complex operation order with front and rear data relevance is split, the invention can effectively reduce the occupied hardware resource, expand the range of the order to be split and improve the performance of the processor.

The invention relates to a digital picture frame capable of processing various audio / video input signals, comprising a power supply unit (201), a display screen (203), a built-in or external storage unit (202), an audio-video / image coding and decoding processor (205), a loudspeaker (209), a display processing unit (204), a sound processing unit (208), an audio / video signal processing unit (206) and an operating instruction processing unit (207), wherein the audio / video signal processing unit (206) is used for separating mutually independent and synchronous audio and video signals from externally input audio / video signals, and the mutually independent and synchronous audio and video signals are transmitted to the loudspeaker (209) and the display screen (203) after being respectively processed by the sound processing unit (208) and the display processing unit (204). The method can process and display externally input audio / video signals with different formats and increase recreational performance.

A computing system can be optimized for high security, reliability and / or integrity. The computing system can include a multiple instruction stream, single data stream processor. The multiple instruction stream, single data stream processor can include a master instruction processing unit, fetch instruction processing units, a single bus interface / memory unit, and a single data processing unit. The computing system can also include a storage device or a memory. The processor can be utilized in numerous applications including avionics software applications.

The invention discloses a low-cost data transmission device for a program counter. An instruction prefetching unit, a predecoding unit, a branch prediction unit and a branch instruction processing unit sequentially form a processing pipeline. The data transmission device further comprises a program counter cache unit and a program counter instruction processing unit. The program counter instruction processing unit is used for transmitting the program counter information of a program counter related instruction to an input port of the program counter cache unit. The branch prediction unit generates a prediction target instruction program counter, and transmits the prediction target instruction program counter and a current instruction program counter to the program counter cache unit. When a branch instruction and the program counter related instruction are executed by the branch instruction processing unit, the program counter information is read from an output port of the program counter cache unit. By the low-cost data transmission device for the program counter, hardware cost in the transmission process of the program counter can be effectively decreased.

A sequencer unit according to embodiments of the present invention comprises a first instruction processing unit, an instruction buffer and a second instruction processing unit. The first instruction processing unit is adapted for receiving and processing a stream of instructions, and for issuing, in case data is required by a certain instruction, a corresponding data read request for fetching said data. Instructions that wait for requested data are buffered in the instruction buffer. The second instruction processing unit is adapted for receiving requested data that corresponds to one of the issued data read requests, for assigning the requested data to the corresponding instructions buffered in the instruction buffer, and for processing said instructions in order to generate an output data stream.

A system includes a disinfection chamber having an interior volume, a radiation source to emit radiation into the interior volume, a radiation sensor circuit to detect radiation in the interior volume, an independent monitoring circuit to detect radiation in the interior volume, and a computing device that has a memory and a processor. The memory stores first radiation values captured by the radiation sensor circuit, second radiation values captured by the independent monitoring circuit, and computer instructions. The processing unit executes the computer instructions to start the emission of radiation, generate first and second accumulated radiation values from the stored values, respectively, and stop the emission of radiation after reaching a first radiation threshold. Based on a comparison of the first accumulated radiation value to the second accumulated radiation value, a validated disinfection signal or an error signal will be asserted.