70 results about "Instruction processing unit" patented technology

The invention relates to the technical field of waste gas treatment, and discloses a digital twinning-based waste gas treatment intelligent early warning system, which comprises a model construction module, a monitoring module, a factor extraction module and the like. The model construction module constructs a dynamic risk model and a three-dimensional concentration field model based on waste gas components and equipment operation state data, and simulates and optimizes parameters in combination; the monitoring module generates a prediction table containing risk indexes and regulation and control parameters; the factor extraction module identifies risk association variables; the evaluation module calculates a risk accumulation index; the adjusting module updates the prediction table in sequence; and the early warning execution module triggers an alarm. The system is also provided with an instruction processing unit for realizing conflict detection and priority management. The system improves the accuracy of risk early warning and the intelligent level of regulation and control, is suitable for industrial waste gas treatment scenes, and guarantees the treatment efficiency and safety.

The embodiment of the invention provides a computing chip and an instruction processing method, and relates to the technical field of integrated circuits, the computing chip adopts a superscalar processor architecture, and comprises an instruction processing unit and a plurality of registers coupled with the instruction processing unit, the plurality of registers comprise a general register and a plurality of private registers respectively coupled with the general register; the general register is used for storing an execution result of a microinstruction which is executed before the jump instruction and is referenced by the microinstruction executed after the jump instruction in a plurality of microinstructions of the calculation task; each private register in the plurality of private registers is used for storing an execution result of any microinstruction in the plurality of microinstructions; the instruction processing unit is used for analyzing each microinstruction in the plurality of microinstructions; and obtaining data in the register according to the analysis result to execute the microinstruction and storing an execution result to the register. According to the embodiment of the invention, the processing efficiency of the processor on the microinstruction can be improved.

Embodiments of this application provide example computing chips and instruction processing method related to the field of integrated circuit technologies. One example computing chip uses a superscalar processor architecture, and includes an instruction processing unit and a plurality of registers that are separately coupled to the instruction processing unit. The plurality of registers include a general purpose register and a plurality of private registers that are separately coupled to the general purpose register. The general purpose register is configured to store an execution result of a microinstruction that is in a plurality of microinstructions of a computing task and that is executed before a jump instruction and whose execution result is referenced by a microinstruction that is executed after the jump instruction. Each private register in the plurality of private registers is configured to store an execution result of any microinstruction in the plurality of microinstructions.

The embodiment of the invention provides a data processing device, a processor and a data processing method. The data processing apparatus includes an instruction distribution unit, an instruction information recording unit, an instruction processing unit, and a write-back control unit, the instruction distribution unit being configured to split a vector instruction into a plurality of microinstructions, and to distribute the plurality of microinstructions to the instruction processing unit; the instruction information recording unit is configured to record instruction state information corresponding to a plurality of microinstructions respectively; the instruction processing unit is configured to receive a plurality of micro-instructions, process each of the plurality of micro-instructions to obtain a corresponding execution result, and feed back a processing progress to the instruction information recording unit; and the write-back control unit is configured to select at least one to-be-written-back microinstruction from the instruction information recording unit to perform write-back operation based on the instruction state information, and the write-back operation is used for writing an execution result of the to-be-written-back microinstruction back to the register. The device can realize out-of-order write-back of the instruction and improve the execution efficiency of the instruction.

The invention relates to the technical field of mouse input control, and discloses an AI intelligent mouse control circuit and an AI intelligent mouse, the circuit comprises a use environment monitoring module and an AI control module, the AI control module comprises: a point location sensing unit, the point location sensing unit is used for sensing a mouse point location at a current use moment; the control chip unit is connected with the point location sensing unit, the use environment monitoring module and the mouse input end, and the control chip unit is used for determining an AI control instruction without a mouse pad based on the mouse use environment and the mouse point location collected by the use environment monitoring module; the AI processing unit is connected with the control chip unit, the AI processing unit is used for determining a detection control instruction based on the AI control instruction, and the control chip unit is further used for determining a mouse input instruction based on the detection control instruction so as to control the AI intelligent mouse based on the mouse input instruction. According to the invention, the functionality of mouse control is improved.

An electric vehicle charging master controller includes an instruction processing unit, a user interface module, and a charging interface module. Electric vehicle (EV) charging equipment is external to the controller. The instruction processing unit is configured to execute instructions for charging electric vehicles (EVs). The charging interface module is configured to receive information from the instruction processing unit and transmit information to the EV charging equipment. The instruction processing unit is configured to transmit information to the charging interface module, which is designed to cause the EV charging equipment to direct charging current to the plurality of EVs, one at a time. The instruction processing unit is also configured to transmit information to the charging interface module designed to cause the EV charging equipment to stop the charging current to each EV when a charging cessation criterion has been met.

The present disclosure relates to a method and a device for generation operation data and a related product, the product comprising a controller unit, and the controller unit comprising: an instruction caching unit, an instruction processing unit and a queue-storing unit. The instruction caching unit is used to store computing instructions associated with artificial neural network operations. The instruction processing unit is used to resolve the computing instructions to obtain a plurality of operation instructions. The queue-storing unit is used to store an instruction queue, which comprises: a plurality of operation instructions or computing instructions to be executed according to the front-to-rear sequence of the queue. Through the above method, the present disclosure may improve the operation efficiency of the related product when carrying out neural network model operations.

The invention discloses a processor, method and system for dynamically switching RISC-V and X86 instruction sets. The processor comprises an instruction reading unit, a translation unit and an instruction processing unit. The instruction reading unit comprises a state machine and a trigger circuit, the instruction reading unit receives an instruction stream and transmits the instruction stream to the state machine, and a target instruction sequence is arranged between any adjacent X86 instruction sequence and RISC-V instruction sequence in the instruction stream; the state machine sends a trigger signal to the trigger circuit when receiving the target instruction sequence, otherwise, the trigger signal is not sent; when the trigger circuit receives the trigger signal, the current state of connecting one of the translation unit and the instruction processing unit is switched to the state of connecting the other one of the translation unit and the instruction processing unit; the translation unit is used for translating the X86 instruction sequence into an RISC-V instruction sequence; the instruction processing unit is used for processing the RISC-V instruction sequence. According to the invention, the RISC-V instruction and the X86 instruction can be dynamically switched and processed.

The present disclosure relates to a data quantization processing method and apparatus, an electronic device, and a storage medium. The apparatus includes a control unit having an instruction caching unit, an instruction processing unit, and a storage queue unit. The instruction caching unit is configured to store a calculation instruction associated with an artificial neural network operation, the instruction processing unit is configured to parse the calculation instruction to obtain a plurality of operation instructions, and the storage queue unit is configured to store an instruction queue. The instruction queue includes a plurality of operation instructions or calculation instructions to be executed in an order of the queue. The above-mentioned method improves the operation precision of related products during a neural network model operation.

The present disclosure relates to a compilation method, apparatus and related products for deep learning algorithms. The product includes a controller unit, and the controller unit includes: an instruction cache unit, an instruction processing unit and a storage queue unit; the instruction cache unit is used to store calculation instructions associated with the artificial neural network operation; the instruction processing unit is used to parse the calculation instructions to obtain a plurality of operation instructions; the storage queue unit is used to store an instruction queue, and the instruction queue includes: a plurality of operation instructions or calculation instructions to be executed in the front-to-back order of the queue. Through the above method, the present disclosure can improve the operation efficiency of related products when performing operations on neural network models.

The invention provides a driving interface module and a use method thereof. The driving interface module comprises an input circuit, an instruction processing unit and an output circuit, the input circuit is used for receiving an instruction sent by the communication card and sending the instruction to the instruction processing unit; the instruction processing unit is used for decoding the instruction, determining a control command of the corresponding electromechanical equipment according to the decoded instruction, and sending the control command to the electromechanical equipment through the output circuit, so that the electromechanical equipment executes the control command; the processor is also used for sending an execution result to the output circuit when receiving the execution result fed back by the electromechanical equipment based on the control command; and the output circuit is used for outputting the execution result to the communication card. The driving interface module is responsible for managing a power supply and a communication interface, ensuring cooperative work with electromechanical equipment, and performing fault and state monitoring; the system can stably operate in high-radiation and extreme environments, and does not depend on a programmable circuit. And by simplifying command management, the operation convenience and the system stability are improved.

The present disclosure provides a data processing apparatus and related products. The products include a control module including an instruction caching unit, an instruction processing unit, and a storage queue unit. The instruction caching unit is configured to store computation instructions associated with an artificial neural network operation; the instruction processing unit is configured to parse the computation instructions to obtain a plurality of operation instructions; and the storage queue unit is configured to store an instruction queue, where the instruction queue includes a plurality of operation instructions or computation instructions to be executed in the sequence of the queue. By adopting the above-mentioned method, the present disclosure can improve the operation efficiency of related products when performing operations of a neural network model.

A communication device includes a processing unit (PROC), a volatile memory (VMEM), a non-volatile storage medium (NMEM) having stored thereon a first set of instructions and a second set of instructions, and a communication unit (COMM) being coupled to the processing unit (PROC). During a transition from a standby mode of operation to an idle mode of operation, the first set of instructions is loaded into the volatile memory (VMEM) enabling the processing unit (PROC) to execute the loaded first set of instructions. During a transition from the idle mode of operation to an active mode of operation, the second set of instructions is additionally loaded into the volatile memory (VMEM) enabling the processing unit (PROC) to execute instructions from the loaded first set of instructions and the loaded second set of instructions. The processing unit is configured, in the idle mode of operation (PROC), to interact with the communication unit (COMM) for detecting, using instructions from the first set of instructions, whether a triggering message is received via the communication unit (COMM), and to initiate the transition from the idle mode of operation to the active mode of operation in response to the detection of the triggering message.

The application provides a remote control decoding device based on a Hamming code, comprising: a shift register, configured to convert acquired serial data based on a clock signal; two code table storage units, respectively configured to store preset Hamming code tables; a count comparison module, configured to intercept corresponding comparison bits based on the clock signal; and a comparator, configured to compare the comparison bits intercepted by the count comparison module with comparison bits corresponding to the serial data, and perform decoding based on preset decoding control logic in the case that a comparison result meets a preset condition, and send a decoding result to a preset instruction processing unit. The remote control decoding device based on the Hamming code does not need to occupy more hardware resources in the case that a code distance requirement is met, and has good universality and expansibility.

A data processing system includes a first subsystem, a second subsystem, a receiving unit, and a processing unit. The receiving unit is configured to receive a configuration instruction. The processing unit is configured to switch the first subsystem and the second subsystem from a first mode to a second mode according to the configuration instruction received by the receiving unit. The first mode is one of an AP mode and an AA mode in which the first subsystem and the second subsystem work, and the second mode is the other of the AP mode and the AA mode in which the first subsystem and the second subsystem work.

The invention belongs to the technical field of ticket business safety access, and provides a ticket business safety access system and method based on terminal network self-adaption and communication channel matching, and the main scheme is as follows: when a ticket buying terminal obtains a query instruction or a ticket buying instruction, the ticket buying terminal sends the query instruction or the ticket buying instruction to a first intermediate server; the first intermediate server performs communication channel matching when receiving a query instruction or a ticket buying instruction, sends the query instruction or the ticket buying instruction to the instruction processing unit behind the communication channel through the matched communication channel, and processes the query instruction or the ticket buying instruction through the instruction processing unit; whether the processed query instruction or ticket buying instruction is forwarded to a ticket service server is judged according to the processing result; and the ticket service server receives the query instruction or the ticket buying instruction processed by the first intermediate server, generates ticket service information in response to the query instruction or the ticket buying instruction, and forwards the ticket service information to the corresponding ticket buying terminal through the first intermediate server or directly sends the ticket service information to the corresponding ticket buying terminal.

A block matrix multiplication operation system relates to a processor, which comprises: an N-bit data bus configured to access a memory; a central processing unit CPU connected to the data bus; a coprocessor coupled to the CPU, the coprocessor comprising a register file having an N-bit register (V); an instruction processing unit in the CPU configured to read access to a memory address in response to a load-spreading machine instruction received by the CPU, and to delegate processing of a corresponding N-bit word (W) presented on the data bus to the coprocessor; and a register control unit in the coprocessor, configured by the CPU in response to the load-spreading instruction to divide the word (W) presented on the data bus into K segments, and write the K segments into the same position in K corresponding registers (V0-V3), the position and the register being specified by the load-spreading instruction.

The present application provides a code compilation method and related devices, which are applied to the central processing unit of an electronic device, the electronic device includes a central processing unit and a parallel processor, the parallel processor includes a scalar instruction processing unit and a vector instruction processing unit, and the method includes: obtaining a target intermediate code to be compiled, the code type of the target intermediate code is a target type, and the target type is used to indicate an intermediate code whose code format is the same as the code format corresponding to any assembly language in a preset assembly language set; compiling the target intermediate code into a target instruction set that can be executed by a parallel processor. In this way, when developers are engaged in related development work on the above-mentioned parallel processor, they can use a simple and easy-to-understand intermediate code type as an intermediate representation of the compilation process, which reduces the development difficulty and promotes the development of software applications on the above-mentioned parallel processor to achieve a parallel processing process with faster processing speed and lower power consumption.

Disclosed are an operandless instruction system-based processor and a computer including same. The operandless instruction system-based processor comprises: an instruction processing unit for processing instructions of a program, wherein the instructions are composed of operandless instructions without operands besides instructions for transmitting and receiving data; one or more function processing units for performing a plurality of functions for data processing; and a stack register for separating instruction processing by the instruction processing unit and data processing by the function processing units. Accordingly, the number of logic gates may be minimized and high efficiency may be maintained by using a simple instruction set that does not include operands.

The invention discloses a processor, a chip product, computer equipment and a data acquisition method, and relates to the technical field of chips. The processor comprises an instruction issuing unit used for splitting a batch instruction into n sub-instructions and issuing the n sub-instructions to an instruction processing unit in sequence, and n is a positive integer larger than 1; and the instruction processing unit is used for multiplexing the instruction related data corresponding to the first sub-instruction into instruction related data corresponding to the second sub-instruction aiming at the second sub-instruction in the n sub-instructions under the condition that the multiplexing mark corresponding to the second sub-instruction is the first mark so as to process the second sub-instruction according to the instruction related data corresponding to the first sub-instruction, the first sub-instruction and the second sub-instruction are adjacent instructions in the n sub-instructions; wherein the first mark is used for indicating that the instruction related data corresponding to the second sub-instruction and the instruction related data corresponding to the first sub-instruction are located in the same register, so that the number of requests for the register is reduced.

The invention provides a computing unit, an instruction fetching request processing method, electronic equipment and a medium. The computing unit comprises an instruction cache unit; the first instruction processing unit is used for generating a first instruction fetching request when a first instruction fetching condition is met, and the first instruction fetching request points to a thread beam-level instruction needing to be acquired; the second instruction processing unit is used for executing work group level instructions, and each work group level instruction comprises a plurality of thread beam level instructions; the instruction fetching request processing unit is used for generating a second instruction fetching request when a second instruction fetching condition is met, the second instruction fetching request points to a working group-level instruction needing to be acquired, arbitrating the first instruction fetching request and the second instruction fetching request according to a preset strategy, selecting one instruction fetching request from the first instruction fetching request and the second instruction fetching request and sending the selected instruction fetching request to the instruction caching unit; and sending the corresponding instruction data to the first instruction processing unit or the second instruction processing unit according to the source of the instruction fetching request. According to the invention, the fetch requests of the work group-level and thread beam-level instructions can be processed in parallel.

The invention provides a bus relay device and an interconnection system supporting simultaneous response to multi-instruction transmission, the bus relay device is used for connecting slave equipment and an interconnection bus, and comprises an instruction processing unit and a cache unit; the instruction processing unit is used for separating and integrating a plurality of received instructions and transmitting the processed instructions to the cache unit; and the cache unit is used for determining direct read-write operation in the cache unit according to the processed instruction, or sending the processed instruction to the slave device for read-write operation. According to the invention, the read-write instructions are separated and integrated, so that the read-write operations are mutually independent and processed in parallel, and the number of read-write access times with an equal relationship is reduced to one, so that repeated read-write is avoided, and the time for processing the instructions is saved; the cache unit supports multi-read and multi-write, read-write instructions from a plurality of master devices can be queried at the same time, and the time for accessing the slave devices is effectively shortened.

An intelligent electronic equipment base comprises a shell, the shell is internally provided with a communication module, and the communication module is used for being in communication connection with electronic equipment and receiving a first instruction sent by the electronic equipment to the communication module; the processing unit is electrically connected with the communication module, the processing unit is used for receiving the first instruction, the processing unit is further in control connection with a driving module, the driving module is used for driving a driven module to act, the driven module further comprises a supporting piece, and the supporting piece is used for supporting electronic equipment; the processing unit is further used for controlling the driving module to work according to the first instruction. The orientation of the electronic equipment is adjusted through linkage of the driven module and the supporting piece. The technical problem that the electronic equipment cannot adjust the orientation is solved.

Provided is an information processing device comprising: an instruction processing unit that inputs, to a language model, a first text which is an authenticity determination target and a second text which instructs an authenticity determination to be performed, and that acquires an authenticity determination result output from the language model; and an evaluation unit that evaluates a hallucination detection performance of the language model on the basis of whether or not the authenticity determination result is correct.

A processing unit is described that receives an instruction to perform a first operation on a first layer of a neural network, block dependency data, and an instruction to perform a second operation on a second layer of the neural network. The processing unit performs the first operation, which includes dividing the first layer into a plurality of input blocks, and operating on the input blocks to generate a plurality of output blocks. The processing unit then performs the second operation after the first operation has generated a set number of output blocks defined by the block dependency data.

The present invention discloses a method for designing flexible meshing of tooth side clearance of a wind turbine yaw bearing. The present invention relates to the field of yaw motor control technology and comprises the following steps: designing a hardware unit for flexible meshing of tooth side clearance of a yaw bearing, setting a yaw instruction processing unit, processing a yaw instruction, establishing a hardware principle block diagram for flexible meshing of tooth side clearance of a yaw bearing, developing a compensation control algorithm for realizing flexible meshing of tooth side clearance of a yaw motor in open-loop and closed-loop working modes and a control process for flexible meshing of tooth side clearance of a yaw bearing. Compared with the traditional method for designing flexible meshing of tooth side clearance of a wind turbine yaw bearing, the method for designing flexible meshing of tooth side clearance of a wind turbine yaw bearing achieves flexible fit between a large gear of a yaw bearing and a small gear of a yaw reducer by means of a software algorithm, without the need to detect tooth side clearance, thereby effectively reducing the risk of gear damage and aggravated mechanical damage due to excessive impact force and inter-tooth force during yaw startup.

The present disclosure relates to a data processing method based on random numbers, a random number generation method and a device, wherein the device includes a control module, wherein the control module includes: an instruction cache unit, an instruction processing unit and a storage queue unit; the instruction cache unit is used to store the calculation instructions associated with the artificial neural network operation; the instruction processing unit is used to parse the calculation instructions to obtain multiple operation instructions; the storage queue unit is used to store an instruction queue, which includes: multiple operation instructions or calculation instructions to be executed in the order of the queue. Through the above method, the present disclosure can improve the operation efficiency of related products when performing operations on neural network models.

This invention provides an image character acquisition device and program that inputs document images, including non-standard documents, and outputs combinations of item names and item values ​​in an easy and appropriate manner. [Solution] The image character acquisition server 1 comprises a document image acquisition unit 11 that acquires document images of documents, an instruction processing unit 12 that inputs the document images acquired by the document image acquisition unit 11 and an item acquisition instruction statement that instructs the AI ​​to extract item names and item values ​​contained in the document images and then acquire combinations of item names and item values, an instruction result acquisition unit 13 that acquires combinations of item names and item values ​​contained in the document images output by the AI ​​as a result of processing by the instruction processing unit 12, and an item combination output unit 14 that outputs combinations of item names and item values ​​acquired by the instruction result acquisition unit 13.

The application provides a data processing system and a chip, and relates to the technical field of data processing. The system comprises a master control unit, an instruction processing unit and a data processing unit. The master control unit is used for issuing a data processing instruction to the instruction processing unit. The instruction processing unit is used for analyzing the data processing instruction to determine the operator type indicated by the data processing instruction, and in the case that the operator type is a non-matrix multiplication-addition operation type, converting the data processing instruction into a data processing micro-instruction of a matrix multiplication-addition operation dimension according to a mapping rule corresponding to the operator type, and writing the data processing micro-instruction into a micro-instruction queue. The data processing unit is used for executing a data processing operation of the matrix multiplication-addition operation dimension according to the data processing micro-instruction in the micro-instruction queue. The chip hardware complexity is effectively reduced, the resource utilization rate and the overall computing efficiency are improved while multiple operators are uniformly accelerated.

The application relates to the technical field of waste gas treatment, and discloses a waste gas treatment intelligent early warning system based on digital twinning, which comprises a model construction module, a monitoring module, a factor extraction module and the like. The model construction module constructs a dynamic risk model and a three-dimensional concentration field model based on waste gas components and equipment operation state data, and combines simulation optimization parameters; the monitoring module generates a prediction table containing a risk index and a regulation parameter; the factor extraction module identifies risk correlation variables; the evaluation module calculates a risk accumulation index; the adjustment module updates the prediction table accordingly; and the early warning execution module triggers an alarm. The system is also provided with an instruction processing unit to realize conflict detection and priority management. The system improves the risk early warning accuracy and the intelligent regulation level, is suitable for an industrial waste gas treatment scene, and guarantees the treatment efficiency and safety.