34 results about "Speculative multithreading" patented technology

Disclosed are selected embodiments of a processor that may include a plurality of thread units and a register file architecture to support speculative multithreading. For at least one embodiment, live-in values for a speculative thread are computed via execution of a precomputation slice and are stored in a validation buffer for later validation. A global register file holds the committed architecture state generated by a non-speculative thread. Each thread unit includes a local register file. A directory indicates, for each architectural register, which speculative thread(s) have generated a value for the architectural register. Other embodiments are also described and claimed.

A system, method and computer program product for supporting thread level speculative execution in a computing environment having multiple processing units adapted for concurrent execution of threads in speculative and non-speculative modes. Each processing unit includes a cache memory hierarchy of caches operatively connected therewith. The apparatus includes an additional cache level local to each processing unit for use only in a thread level speculation mode, each additional cache for storing speculative results and status associated with its associated processor when handling speculative threads. The additional local cache level at each processing unit are interconnected so that speculative values and control data may be forwarded between parallel executing threads. A control implementation is provided that enables speculative coherence between speculative threads executing in the computing environment.

A system, method and computer program product for supporting thread level speculative execution in a computing environment having multiple processing units adapted for concurrent execution of threads in speculative and non-speculative modes. Each processing unit includes a cache memory hierarchy of caches operatively connected therewith. The apparatus includes an additional cache level local to each processing unit for use only in a thread level speculation mode, each additional cache for storing speculative results and status associated with its associated processor when handling speculative threads. The additional local cache level at each processing unit are interconnected so that speculative values and control data may be forwarded between parallel executing threads. A control implementation is provided that enables speculative coherence between speculative threads executing in the computing environment.

A method for analyzing a set of spawning pairs, where each spawning pair identifies at least one speculative thread. The analysis may be practiced via software in a compiler, binary optimizer, standalone modeler, or the like. The analysis may include determining a predicted execution time for a sequence of program instructions, given the set of spawning pairs, for a target processor having a known number of thread units, where the target processor supports speculative multithreading. The method is further to select a spawning pair, according to a greedy approach, if the spawning pair provides a performance enhancement, in terms of decreased execution time due to increased parallelism, when the speculative thread is spawned during execution of a code sequence. Other embodiments are also described and claimed.

Verifying speculative multithreading in an application executing in a computing system, including: executing one or more test instructions serially thereby producing a serial result, including insuring that all data dependencies among the test instructions are satisfied; executing the test instructions speculatively in a plurality of threads thereby producing a speculative result; and determining whether a speculative multithreading error exists including: comparing the serial result to the speculative result and, if the serial result does not match the speculative result, determining that a speculative multithreading error exists.

The present subject-matter belongs to the field of system and methods for automatic and electronic transaction control, namely in introducing minimum holding times and forcing transaction outcomes in a market. The system and method include adjusting asset value and availability for mitigating speculative market manipulation and pure speculative trading transactions outcomes in a prediction market. The modules introduce pure delays, selective delays or force the transaction outcome evaluations such that these goals are addressed. One of the principles used in these methods and modules is that by increasing the risk of the purely speculative or manipulative trading strategies, their expected payoff will be reduced. Thus participants will have less incentive to use them and their occurrence and impact will be greatly reduced.

The invention discloses a speculative multithreading division method based on machine learning. The speculative multithreading division method comprises the following steps: extracting program characteristics from an irregular program set, and combining a CFG (Control Flow Graph) with comments with a key path to show the program characteristics; then, constructing a program CFG by a SUIF compiler, converting the program CFG into a weighted CFG and a super block CFG, carrying out threading division, which aims at a cyclic part and an acyclic part, on the program set to obtain a training sample set formed by the program characteristics and an optimal division scheme; and finally, extracting the characteristics of an irregular program to be divided, calculating similarity between the characteristics of the irregular program to be divided and the program characteristics in the training samples, and carrying out weighted calculation on the division threshold values of a plurality of most similar sample programs to obtain an optimal division scheme suitable for the irregular program. The similarity between the program to be divided and the sample program is compared on the basis of the program characteristics, a similar sample division scheme is applied to the program to be divided, and therefore, the speculative multithreading division method exhibits better adaptability on each class of parallel irregular programs.

A method for rolling back speculative threads in symmetric-multiprocessing (SMP) environments is disclosed. In one embodiment, such a method includes detecting an aborted thread at runtime and determining whether the aborted thread is an oldest aborted thread. In the event the aborted thread is the oldest aborted thread, the method sets a high-priority request for allocation to an absolute thread number associated with the oldest aborted thread. The method further detects that the high-priority request is set and, in response, clears the high-priority request and sets an allocation token to the absolute thread number associated with the oldest aborted thread, thereby allowing the oldest aborted thread to retry a work unit associated with the absolute thread number. A corresponding apparatus and computer program product are also disclosed.

A method, a system and a computer program product for effectively accelerating loop iterators using speculative execution of iterators. An Efficient Loop Iterator (ELI) utility detects initiation of a target program and initiates / spawns a speculative iterator thread at the start of the basic code block ahead of the code block that initiates a nested loop. The ELI utility assigns the iterator thread to a dedicated processor in a multi-processor system. The speculative thread runs / executes ahead of the execution of the nested loop and calculates indices in a corresponding multidimensional array. The iterator thread adds all the precomputed indices to a single queue. As a result, the ELI utility effectively enables a multidimensional loop to be replaced by a single dimensional loop. At the beginning of (or during) each iteration of the iterator, the ELI utility “dequeues” an entry from the queue to use the entry to access the array upon which the ELI utility iterates. The ELI utility performs concurrent iterations on the array by using the queue entries.

The invention discloses an improved thread level speculation (TLS) method and an improved TLS device. The method comprises the following steps of: acquiring a thread speculation message in a network message, and distinguishing and arranging the priorities of access request messages which are sent by a previous thread and a subsequent thread to determine a priority sequence, wherein the priority of the access request message which is sent by the previous thread is higher than that of the access request message which is sent by the subsequent thread; and transmitting the corresponding access request messages to directory nodes according to the determined priority sequence, and reading or writing data at the directory nodes. By adoption of the method provided by the invention, the priorities of access requests in the thread speculation message are distinguished, the priorities of a plurality of threads in a program are distinguished, and the data at the directory nodes can be read or written according to the priority sequence, so squash of the threads is avoided, the squash rate of the threads and the power consumption of TLS are reduced, and the performance of the TLS is stabilized and improved.

The invention discloses a CMP (Chip Multiprocessor)-based multi-speculative path thread partitioning method under a speculative multithreading mechanism. According to the method, a process is taken as a unit in thread partitioning; for each process, control-independence nodes of thread end points in the process are limited during partitioning; mutual exclusion path segments of thread excitation points in the process are limited, so that excitation of the thread is relatively strictly limited; meanwhile, the excitation points on the mutual exclusion path segments are made to correspond to the same thread end point; a plurality of continuous pre-computation slices are inserted behind the thread end points; the contents of the pre-computation slices are mutually different along with the changes of the speculative paths and the excitation points; and a simulator carries out different speculative paths when running, and selects corresponding pre-computation slices for executionaccording to the corresponding excitation points on the speculative paths. According to the method, thread partitioning can be carried out on a plurality of paths, so that the branch coverage rate of speculative parallel execution is increased.