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Low complexity speculative multithreading system based on unmodified microprocessor core

a microprocessor core and low complexity technology, applied in the direction of memory architecture accessing/allocation, instruments, computing, etc., can solve the problems of limited performance gain by exploiting ipl, complex process, and limited success of parallelizing compilers in automatically handling these tasks

Inactive Publication Date: 2007-08-16
IBM CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0041] Re-starting one or more threads if a violation has been identified, and ensuring correct use of input values for restarted thread.

Problems solved by technology

The arising challenge is to find the most effective way to put these transistors to use.
However, the possible performance gain by exploiting IPL is limited due to the finite amount of ILP present in any particular application sequence.
However, many important existing applications are written for uniprocessors, and it is a non-trivial task to convert uniprocessor applications into multiprocessor ones.
So far, parallelizing compilers have had only limited success at automatically handling these tasks.
This process is complex because it is necessary to determine all possible true dependencies in a program before synchronization points may be inserted.
In many programs there are many potential dependencies that may result in a true dependency, but where dependencies rarely if ever actually occur during the execution of the program.
By requiring significant changes to the processor core and / or to the memory nest to enable thread level speculation, existing architectures cannot take advantage of the increased performance potential which TLS offers.
Similarly for the memory nest, re-design and verification effort makes it prohibitive, or at least very expensive, for already existing cores and system.
This is significantly less flexible than the previously described approach which separates a program into a sequence of threads.
The cited patent does not require state buffering, or thread re-start as the model does not support coherent speculative multithreading.

Method used

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  • Low complexity speculative multithreading system based on unmodified microprocessor core
  • Low complexity speculative multithreading system based on unmodified microprocessor core
  • Low complexity speculative multithreading system based on unmodified microprocessor core

Examples

Experimental program
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Embodiment Construction

[0059] With reference to the accompanying drawings, FIG. 1 illustrates a schematic diagram of the overall base architecture of the multiprocessor system 10 without the support for thread level speculation. The system is composed of four identical processor cores labeled CPU0 to CPU3, labeled 100-103, respectively, each with associated local L1 level data and instruction caches, labeled 110-113, respectively, and their associated L2 caches 120-123, respectively. The system's L3 cache 130 is shared and can be implemented on-chip or off-chip. In the preferred embodiment, the processor cores 100-103 are PowerPC cores such as PPC440 or PPC405, but any other processor core can be used without departing from the scope of this invention. The processor cores 100-103 are interconnected by a processor local bus 150. In addition, the architecture also includes a shared multi-ported SRAM 140.

[0060]FIG. 2 shows the addition of the new cache level L1.5 between the data caches L1 and L2 levels to ...

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PUM

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Abstract

A system, method and computer program product for supporting thread level speculative execution in a computing environment having multiple processing units adapted for concurrent execution of threads in speculative and non-speculative modes. Each processing unit includes a cache memory hierarchy of caches operatively connected therewith. The apparatus includes an additional cache level local to each processing unit for use only in a thread level speculation mode, each additional cache for storing speculative results and status associated with its associated processor when handling speculative threads. The additional local cache level at each processing unit are interconnected so that speculative values and control data may be forwarded between parallel executing threads. A control implementation is provided that enables speculative coherence between speculative threads executing in the computing environment.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] The present application is based on applicants' commonly-owned, co-pending United States Patent Application No. ______ [YOR920040626US1, D#18469] filed on ______ and entitled ARCHITECTURAL SUPPORT FOR THREAD LEVEL SPECULATIVE EXECUTION, the contents and disclosure of which is incorporated by reference as if fully set forth herein.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention generally relates to microprocessor and multiprocessor architectures and, more particularly, to thread-level speculative processor execution for achieving high performance and speeding up sequential applications. [0004] 2. Description of the Prior Art [0005] As increasing numbers of smaller and faster transistors can be integrated on a single chip, new processors are designed to use these transistors effectively to increase performance. The arising challenge is to find the most effective way to put these transistors to use...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F13/28
CPCG06F9/3842G06F9/3851G06F9/3828G06F12/0815G06F2212/507G06F12/0811
Inventor GARA, ALAN G.GSCHWIND, MICHAEL K.SALAPURA, VALENTINA
Owner IBM CORP
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