Low complexity speculative multithreading system based on unmodified microprocessor core
a microprocessor core and low complexity technology, applied in the direction of memory architecture accessing/allocation, instruments, computing, etc., can solve the problems of limited performance gain by exploiting ipl, complex process, and limited success of parallelizing compilers in automatically handling these tasks
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[0059] With reference to the accompanying drawings, FIG. 1 illustrates a schematic diagram of the overall base architecture of the multiprocessor system 10 without the support for thread level speculation. The system is composed of four identical processor cores labeled CPU0 to CPU3, labeled 100-103, respectively, each with associated local L1 level data and instruction caches, labeled 110-113, respectively, and their associated L2 caches 120-123, respectively. The system's L3 cache 130 is shared and can be implemented on-chip or off-chip. In the preferred embodiment, the processor cores 100-103 are PowerPC cores such as PPC440 or PPC405, but any other processor core can be used without departing from the scope of this invention. The processor cores 100-103 are interconnected by a processor local bus 150. In addition, the architecture also includes a shared multi-ported SRAM 140.
[0060]FIG. 2 shows the addition of the new cache level L1.5 between the data caches L1 and L2 levels to ...
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