212 results about "Precomputation" patented technology

Workloads for executing a graph neural network (GNN) may be divided among various processing units, such as a central processing unit (CPU) and a neural processing unit (NPU). The NPU may include a data processing unit (DPU) and a digital signal processor (DSP). The CPU may perform precomputation, model optimization, hardware optimization, and compilation. For example, the CPU may precompute a parameter matrix and use the parameter matrix as internal parameters of a GNN. The CPU may also perform node padding, approximation computation, or transfer of DSP operations to DPU to optimize the GNN. The CPU may also perform sparsity data compute and storage, vertical fusion of DSP operations and DPU operations, or data quantization to optimize performance of the NPU. The compiled GNN may be provided to the NPU, and the DPU and DSP may perform the operations in the compiled GNN to produce a prediction of the GNN.

Latency, response times, and efficiency improvements for data querying are provided herein, particularly in the context of querying large database systems and data tables from disparate data sources. There are provided systems and methods for automatic query and data retrieval optimization through procedural generation of data tables from query patterns. A service provider may utilize different computing services for query processing and data retrieval for different applications and services used by internal and / or external users. Instead of querying large database systems and numerous data tables, pre-aggregated data tables may instead be used and searched by procedurally generating such tables based on precomputation rules and query patterns. Once patterns have been identified in queries, corresponding data may be aggregated from data sources in a pre-aggregated data table. Query optimization rules may then be used to have these data tables queried in place of their original sources.

This specification discloses systems and methods for enhancing the efficiency of transformer models during inference and training by precomputing and storing in memory a significant portion of operations in the first transformer layer. The stored precomputed outputs are retrieved from memory during runtime, reducing computational complexity and memory bandwidth requirements. This approach results in decreased latency, increased throughput, and lower cost-per-token. The disclosed techniques are particularly advantageous for transformer models that incorporate positional encodings within the attention mechanism, such as Rotary Position Embedding (RoPE) and other relative position encoding schemes. The method of offline precomputing involves calculating the outputs of the eliminated operations and components for each of the original vocab_size embedding-vectors, where vocab_size is the size of the embedding vocabulary. One embodiment of the invention removes the feedforward network and the attention query, key, and value projections from the first transformer layer of the encoder and the decoder stacks.

The invention belongs to the technical field of storage and calculation integration, and particularly relates to a low-bit-width and high-energy-efficiency floating point storage and calculation integrated circuit based on a partial pre-alignment framework. The circuit comprises a memory array, a pre-calculation unit, an adder tree, a configurable arithmetic unit and a normalization unit, and supports mixed precision operation of FP8MACFP4 and FP8MACFP8. The method is characterized in that a partial pre-alignment strategy dominated by an activation value is adopted, the maximum index of the activation value is dynamically counted, the mantissa of the maximum index is aligned, and multiple partial pre-alignment intermediate results are pre-calculated and latched for reuse; in combination with a customized lookup table and a multiplexer, a pre-calculation result is directly selected to replace real-time multiplication and displacement; and through the reconfigurable hardware, the FP8MACFP8 high-precision operation is realized by utilizing the FP8MACFP4 unit combination. According to the method, complete online floating point multiplication and addition operation is realized, and excellent energy efficiency ratio and operation speed are obtained while high precision is kept.

The invention discloses a multi-modal KV cache retrieval method and system based on a hybrid architecture, relates to the technical field of data processing, and aims to solve the technical problem that in the prior art, due to the adoption of a full-online computing architecture and lack of a unified cross-modal representation framework, the computing efficiency and the modal fusion effect are difficult to consider at the same time. By constructing a hybrid processing architecture of offline pre-calculation and online processing, multi-modal data is subjected to unified fragmentation coding and KV cache and semantic fingerprints of the multi-modal data are pre-calculated in an offline stage, and cache fragments are intelligently assembled and position codes are dynamically remapped based on a user query intention in an online stage; therefore, online repeated calculation of multi-modal content is fundamentally avoided, coherent alignment and efficient fusion of cross-modal semantics are achieved, the real-time response capability, the cache reuse rate and the multi-modal generation quality of the system are remarkably improved, and high-concurrency scenes can be dynamically adapted.

The invention provides a lightweight deployment method and system of a large model on edge computing equipment. According to the method, the acceleration capability portrait is constructed by extracting the hardware instruction set architecture type of the target edge device and the number of parallel computing units. Based on the instruction type, the large model weight is grouped, divided and pre-calculated through a unified lookup table vectorization engine, and a pre-calculation vector matched with the target instruction set is generated; and according to the number of the parallel units and the instruction-level parallel capability, compiling the pre-calculation vector to generate an adaptive parallel table look-up instruction block, distributing execution threads with the same number as the parallel units, and eliminating data dependence conflicts. And finally, loading the instruction block to a shared memory area, configuring topological logic of the photoconductive switch matrix based on an instruction type, and dynamically switching a data transmission path in a hardware instruction period. According to the method, the efficient deployment of the large model in the edge equipment and the low-delay reasoning in the resource-constrained environment are realized.

The invention provides a generative intelligent optimization method and device, and relates to the technical field of generative artificial intelligence optimization computation.The method comprises the steps that a mathematical model containing decision variables, an objective function and constraint conditions is established for a target optimization problem, and scene parameters are pre-calculated through a traditional optimization algorithm to obtain a theoretical optimal solution; constructing a training data set containing scene parameters and a theoretical optimal solution; training the data set through a conditional generation type artificial intelligence model, minimizing the difference between a generation decision and a theoretical optimal solution, and establishing a mapping relation from scene parameters to an optimal decision, so that the mapping relation implicitly learns a constraint condition satisfaction mode; current scene parameters are collected in real time and input into the trained model, a near-optimal decision scheme is generated through reverse denoising or hidden variable decoding, and the near-optimal decision scheme is applied to real-time scenes such as industrial control. According to the method, a high-quality solution close to theoretical optimum is realized, the online solution time consumption is remarkably reduced, and the real-time requirement is met.

The invention provides a communication optimization method for topological table persistent storage in efficient parallel computing, belongs to the technical field of storage communication, and aims to avoid pseudo sharing by aligning memory allocation through cache lines, expand local topological coverage through a topological entropy increment driven prefetching mechanism, and improve the reliability of the topological table persistent storage. Boundary processing is accelerated through a pre-calculation period mapping lookup table and a frequency domain transfer function vector, synchronization overhead is optimized through a concurrency control mechanism perceived by a read-write ratio, targeted cache preloading is achieved through stability and jitter degree two-dimensional evaluation, bandwidth consumption is reduced through an increment synchronization mechanism, and the stability of the cache is improved. The communication template is selected or the communication parameters are generated through adaptive conversion by matching the matching degree decision, and the technical problem that the parallel computing performance is reduced due to the fact that the communication overhead is too large in the topological table persistent storage process is solved.

The invention discloses a multi-scalar multiplication acceleration method based on resource estimation and a pre-calculation strategy, and provides a systematic solution for the problems of insufficient resource estimation, pre-calculation factor stiffness and low sorting efficiency of a Pippenger algorithm in zero-knowledge proof. A multi-resolution point multiplication table is dynamically generated through a hierarchical displacement pre-calculation strategy, and global memory access delay is remarkably reduced by combining memory layout optimization and asynchronous flow task scheduling of window inner barrel continuous storage. A dynamic resource adaptation mechanism is designed, thread block topology, grid division and sorting algorithm selection are adjusted in real time based on GPU hardware features, and load balancing and cache utilization rate maximization are achieved. Iterative reduction and double temporary bucket strategies are introduced, and data scale is compressed and boundary processing is optimized through multi-round reduction. In the large-scale MSM operation in the block chain and privacy computing field, the computing efficiency and the resource utilization rate can be remarkably improved, and the method is suitable for an elliptic curve cryptography acceleration task.

The embodiment of the invention provides a cyclic redundancy check method and device, electronic equipment and a medium. The method comprises the following steps: determining a target pre-calculation result according to a target parameter; the target parameter comprises a target generator polynomial and a target data bit width; the target pre-calculation result comprises a cyclic redundancy check (CRC) input coefficient matrix and an input data coefficient matrix; determining a parallel CRC calculation logic according to the target pre-calculation result; the parallel CRC calculation logic is used for calculating a CRC check result of each check cycle in each check cycle; and updating the to-be-verified system according to the parallel CRC calculation logic, and when the to-be-verified system receives the to-be-verified data, controlling the to-be-verified system to execute the parallel CRC calculation logic to verify the to-be-verified data to obtain a verification result. The method is used for achieving the effect of efficiently determining the parallel CRC calculation logic applied to the to-be-verified system.

The invention discloses a resource allocation method and device based on bit map pre-calculation, and the method comprises the steps: generating a global resource state bitmap according to the CORESET configuration in a PDCCH, and carrying out the pre-calculation of each possible candidate PDCCH to form a candidate pre-allocation bit map set; extracting a corresponding pre-allocation bitmap from the candidate pre-allocation bitmap set as a candidate set bitmap; and comparing the candidate set bitmap with the global resource state bitmap, judging whether the resources are conflicted or not, and if the resources are not conflicted, determining that the resources are available and further occupying the resources. Complex function calculation at the scheduling moment is transferred to pre-calculation at the initialization stage, only simple bitmap retrieval and bit operation are needed during scheduling, the PDCCH resource allocation time consumption is greatly shortened, real-time intensive calculation is replaced with pre-stored bitmaps, the CPU load is remarkably reduced, a processor focuses on a core scheduling algorithm, resource redundancy consumption is reduced, and the scheduling efficiency is improved. And the overall capacity and the energy utilization efficiency of the communication system are effectively improved.

The invention provides an ML-DSA module reduction method and device based on improved Barrett reduction, and the method comprises the steps: dividing an input signal into a first preset bit signal and a second preset bit signal according to the bit width, and carrying out the shift addition operation of the first preset bit signal, so as to generate a middle quotient value; generating a first preset bit remainder based on the intermediate value; performing splicing processing on the first preset bit remainder and the second preset bit signal to generate an intermediate remainder; and performing a correction operation on the intermediate remainder to output a remainder result. According to the operation method, an input signal is processed in a high-order mode and a low-order mode, and the bit width participating in multiplication and shifting operation is reduced; according to the method, a precomputation constant is optimized, the number of times of addition is reduced, and wide bit operation in a critical path is eliminated by means of segmentation processing and register insertion, so that the critical path is shortened, and the maximum operation frequency of a system clock is improved; and through error analysis and range limitation, the correctness of a module reduction result is ensured.

The invention provides an NoC low-delay data transmission method based on a dynamic routing algorithm, relates to the technical field of data transmission, and aims to solve the technical problems that an existing NoC routing algorithm cannot adapt to a link dynamic load, is lack of congestion trend prejudgment, is slow in path search convergence and is insufficient in QoS differential scheduling. The method comprises the following steps: constructing a dynamic sensing module containing a double-branch LSTM time sequence prediction model, collecting states such as link bandwidth and queue length in real time, and predicting a congestion trend in 50-100ms in the future; constructing a multi-objective evaluation function taking delay as a core, and dynamically adjusting the weight according to the QoS level; solving an optimal path by adopting an improved ant colony algorithm which introduces a congestion penalty and pruning strategy; during transmission, dynamic reselection is triggered through a pre-calculation + fast matching mechanism; and iteratively optimizing the prediction model based on incremental learning. According to the method, congestion is avoided in advance, the path search efficiency and the transmission reliability are improved, the delay is remarkably reduced compared with a traditional algorithm, and the method is adaptive to delay sensitive scenes such as a high-performance processor and an AI chip.

Provided in the present application is a fast modular multiplication system based on base transformation. The fast modular multiplication system comprises: a precomputation layer, which is used for performing base transformation processing on a first modular multiplication input A and a second modular multiplication input B, which are inputted; a polynomial modular multiplication layer, which is used for sequentially performing grouped multiplication processing and recombination and reduction processing on the first modular multiplication input A and the second modular multiplication input B which have been subjected to base transformation processing; an iterative reduction layer, which is used for sequentially performing several instances of mapping and wiring processing and accumulation processing on a polynomial which has been subjected to the recombination and reduction processing and includes the first modular multiplication input A and the second modular multiplication input B; and a radix restoration layer, which is used for converting, from a radix-X to binary, a polynomial which has been subjected to the last instance of accumulation processing and includes the first modular multiplication input A and the second modular multiplication input B. In the present application, the fast modular multiplication system reduces the usage of circuit hardware, and thus the area of a circuit is saved on, and more advantages in terms of both area and speed exist compared with a conventional modular multiplication system.

An on-loop efficient multiplication optimization method based on a sparse ternary polynomial and precomputation belongs to the field of cryptography and comprises the following steps: compressing a cyclic matrix of a prime order domain loop into a single row to obtain a generation operator matrix temp; storing the second column of elements in the temp in an inverted sequence; according to the sparse property of a ternary polynomial and the algebraic structure characteristic of a finite ring (Z / q) [x] / (xp-x-1), through sparse coefficient traversal, table look-up operation is carried out on non-zero coefficients of the ternary polynomial. According to the method, traditional NTT multiplication is replaced by addition and subtraction, the sparse small polynomial characteristics are combined, the theoretical complexity of polynomial multiplication is reduced to be close to O (p) from O (p2), and the operation efficiency is remarkably improved; a compression type precomputation cyclic matrix and a reverse storage strategy are adopted, memory occupation is reduced, the resource utilization rate is improved, the application scene is expanded, and flexibility and practicability are remarkably improved.

The invention discloses a privacy protection neural network reasoning method based on multi-point evaluation. According to the method, in the reasoning process of the privacy protection neural network, a given nonlinear function is constructed into a K-segment k-degree polynomial, a safe multiplication tree and a safe remainder tree are established, and then the remainder polynomial is safely evaluated. Due to the fact that the polynomial power needing to be evaluated in the online stage is reduced, the number of self-multiplication terms is reduced, the number of communication rounds of overall polynomial evaluation is reduced, the number of calling times of a secure multiplication triple in secret sharing is reduced, and the overhead of offline pre-calculation is correspondingly reduced. In addition, the hierarchical structure of the secure multiplication tree and the remainder tree supports multi-point input parallel computing, and the parallel computing capability of a modern multi-core processor or a GPU can be fully utilized.

A system and method for adaptive ideation and innovation management using graph-based similarity computation and real-time social facilitation are disclosed, and the system may include a plurality of client devices operated by a human user and one or more AI Agents. The system may further include a computing platform running a Precompute Similarity Engine that may be configured to embed and index idea objects, precompute similarity clusters, and generate candidate merge or purge operations together with diversity and novelty signals; and running a Social Physics Engine that may be configured to monitor human user and machine participant (AI agent) interactions, compute group metrics, and issue digital facilitation interventions. The Precompute Similarity Engine and the Social Physics Engine may operate in an interdependent feedback loop such that diversity and novelty signals guide the generation of digital facilitation interventions that are communicated via the network to the plurality of client devices and the one or more AI Agents.

The invention belongs to the technical field of network communication. The invention provides a hardware implementation method and device of an IPSec protocol processor based on an ASCON lightweight encryption algorithm. According to the embodiment of the invention, the ASCON lightweight encryption algorithm and the optimized security policy matching algorithm are introduced, the high throughput rate is ensured, the resource consumption is reduced, the delay is reduced, the hardware implementation of the ASCON algorithm is optimized for the application scene of IPSec protocol processing, and the whole flow of the ASCON algorithm is divided into two stages of pre-calculation and message encryption, so that the processing efficiency of the IPSec protocol is improved. By pre-calculating and storing the initialization of each security alliance and the encryption intermediate state of the associated data, repeated calculation is avoided, and the throughput is improved by executing multiple turns of transformation in parallel in a single cycle in the hardware implementation of the message plus module.

The invention discloses an elliptic curve scalar multiplication optimization method, an elliptic curve scalar multiplication optimization device and elliptic curve scalar multiplication optimization equipment based on multiple windows and multiple base chains, which can be used for a communication system core network. The method comprises the steps that parameter sets arranged according to the window width in a descending order are configured, each parameter set comprises a cardinal number set and the window width w, and a corresponding candidate odd number set is generated; sliding recoding is carried out on an input scalar k, 0 is added to even-numbered bits and the even-numbered bits are shifted rightwards by k, a congruent recoding number with the minimum absolute value is searched for odd-numbered bits according to the priority of a parameter group, if the recoding number is not found, the wNAF rule is returned, and a sparse digital sequence D is obtained; according to a fast / ct mode, generating a pre-calculation lookup table by combining a power chain with a binary combination; and scanning D from a high order to a low order, sequentially executing point doubling operation by the accumulator, executing conditional point adding operation when meeting a non-zero number, and finally obtaining a scalar multiplication result. According to the method, the non-zero bit density and the side channel risk are reduced, the operation efficiency is improved, and the method is suitable for various security scenes.

The invention provides a lightweight elliptic curve cryptographic reconfigurable processor. The reconfigurable computing unit array comprises a shared data area and a reconfigurable instruction memory, the shared data area is used for an upper layer system to write initial data, global configuration parameters, two sets of moduli, two sets of pre-computing parameters Mu and to-be-computed data, the initial data comprises elliptic curve configuration parameters and a group of noise data, and the global configuration parameters comprise reconfigurable data of the computing unit array; the reconfigurable instruction memory is used for an upper-layer system to write reconfigurable instructions, and the reconfigurable instructions comprise an initialization instruction, an operation instruction and a jump instruction. The method can cope with application scenes such as high security, low power consumption, rapid switching and reconstruction of the ECC algorithm, can be flexibly applied to the fields of national password security, network security teaching and commercial password, and has a wide application prospect.

The invention discloses a neutral atom quantum compiling method and system for off-line pre-calculation, and belongs to the field of quantum computation.The method comprises the two stages of off-line template construction and on-line compiling, specifically, in the off-line stage, a neutral atom array is abstracted into a two-dimensional grid, an effective gate candidate set is constructed based on the Rydberg blocking radius and the parallel execution limiting radius, and an effective gate candidate set is constructed based on the effective gate candidate set; generating a space template configured by the maximum parallel gate by using a satisfiability model theory solver, and expanding a template library through rotational symmetry; in the online stage, quantum circuits are layered, matching templates are retrieved, slot distribution, direction selection and conflict evaluation are carried out, and finally an executable operation sequence is generated through timing sequence routing coloring. According to the method, the compiling efficiency, the expandability and the circuit execution fidelity are remarkably improved, and the method is suitable for a large-scale neutral atom quantum computing platform.

A method for countering a profiling of deep-learning side channel (SCA) algorithm to disrupt a training phase of a deep-learning model is provided. It alters and interleaves an execution sequence of modular exponentiations or point additions in a counter SCA algorithm. The mixing, loops through bits of a private key, D, along a sliding window, wherein for each loop, an N-bit tuple from the private key is compared to the random number plus a linear increment, and, if the value is a match, it indexes into said precomputed vector according to said random number, r, thereby extracting and interleaving values into an execution path of said counter SCA algorithm from said precomputed vector according to an index represented by said random number; otherwise. Other embodiments are provided.

Described herein is NLS using a bounded linear initial search space and a fixed grid with pre-calculated variables. Specifically, first and second signals with unknown first and second elevation angles, respectively, are received that have been reflected by an object, with the second signal also having been reflected off the ground. A line of second angles is then established as a function of first angles, a sensor height, and a range to the object. The first angles being bound by a function of the sensor height and the range and a function of the sensor height, the range, and the maximum height. A search algorithm is then used to search for an initial elevation angle pair along the line. The initial elevation angle pair may then be fed into a refinement algorithm (e.g., non-linear least squares) to determine the elevation angles associated with the first and second signals.

The invention discloses a multi-machine four-dimensional cooperative path planning method for pre-calculating a deviation path and dynamically re-planning, and belongs to the field of cooperative control and path planning of unmanned aerial vehicle clusters. The method comprises the following steps: dividing a three-dimensional airspace into cubic empty blocks, constructing a directed connected graph, and removing the empty blocks and edges which do not meet a safe distance; generating an initial three-dimensional path of each unmanned aerial vehicle by using a dynamic priority fast expansion random tree algorithm; taking an end point empty block as a starting point, constructing a reverse reachable graph by means of breadth-first search, pre-calculating a plurality of deviation paths from a neighborhood empty block to an end point in an off-line manner, and storing the deviation paths into the empty block; when a dynamic threat is detected in the task, calling an improved heuristic artificial potential field algorithm to generate a local obstacle avoidance section; and retrieving a pre-stored deviation path after obstacle avoidance, and selecting an optimal path for splicing in combination with a cost function. According to the method, the calculation amount is moved forward to an offline stage, the dynamic environment re-planning time is shortened, simultaneous arrival of multiple machines and space safety are guaranteed, and the expansion capability and the real-time performance are improved.

The invention discloses a lens vignetting correction method and device, computer equipment and a storage medium, and the method comprises the steps: setting a reference data index according to a vignetting intensity parameter of a lens, and extracting a reference coefficient from pre-calibrated lens vignetting data; constructing a correction lookup table in combination with the vignetting intensity parameter, the reference data index and the reference coefficient; obtaining a target image collected by a lens, and calculating an optical center coordinate and a normalized radius reference value of the target image; obtaining a to-be-processed area of the target image, and performing area initialization on the to-be-processed area in combination with the optical center coordinate and the normalized radius reference value; and based on the initialized to-be-processed region, correcting the target image in combination with the correction lookup table. According to the vignetting correction method and device, the real-time complex mathematical operation is converted into the pre-calculated table query operation, efficient and accurate vignetting correction is achieved, and the problems that in the prior art, calculation complexity is high, and real-time performance is poor are solved.

Latency, response times, and efficiency improvements for data querying are provided herein, particularly in the context of querying large database systems and data tables from disparate data sources. There are provided systems and methods for automatic query and data retrieval optimization through procedural generation of data tables from query patterns. A service provider may utilize different computing services for query processing and data retrieval for different applications and services used by internal and / or external users. Instead of querying large database systems and numerous data tables, pre-aggregated data tables may instead be used and searched by procedurally generating such tables based on precomputation rules and query patterns. Once patterns have been identified in queries, corresponding data may be aggregated from data sources in a pre-aggregated data table. Query optimization rules may then be used to have these data tables queried in place of their original sources.

This invention relates to the field of data processing technology, and in particular to a method, apparatus, device, and medium for processing multi-dimensional data. The method instantiates a template based on input tensor parameters to obtain an offset calculation instance. The offset calculation instance is initialized to determine the step size and shape of each input array in each output dimension, and these are recorded in a designated storage space. The offset calculation instance is then started to perform index calculations on the step size and shape of each input array recorded in the storage space in each output dimension to obtain the offset corresponding to the output array. The data corresponding to the offset is then processed according to a set calculation rule to obtain the output result. By pre-calculating the step size and shape of each input array in each output dimension, unnecessary memory accesses can be reduced. Constructing offset calculation instances simplifies the index calculation process, enabling efficient and accurate data storage, retrieval, and calculation.

The disclosure is directed to a method including executing, at a first time, a precompute algorithm that is a first portion of a quantum algorithm. Executing the precompute algorithm generates a precompute output that includes first quantum information encoded in a first set of qubits. A runtime input for the quantum algorithm is received at a second time that is subsequent to the first time. A runtime algorithm is executed, at a third time that is subsequent to the second time. The runtime algorithm is a second portion of the quantum algorithm. Executing the runtime algorithm is based on the first quantum information encoded in the first set of qubits. Executing the runtime algorithm generates a runtime output that includes second quantum information encoded in a set of qubits. An output of the quantum algorithm is provided. The output of the quantum algorithm is based on the second quantum information.

The invention relates to the technical field of big data, and provides a transaction data processing method and device based on idle time, equipment and a medium, which can start a business thread to scan a market queue and a return queue in real time in a current transaction period so as to respond in time. In the continuous scanning process of preset times, when no new market information slice is scanned in the market information queue and no new return information is scanned in the return queue, calculating the current idle time according to an idle time determination strategy after the market information and the return are ensured to be processed; the operator type with high real-time performance is divided into the pre-calculation operator and the decision operator, the pre-calculation operator is processed in the current idle time, the decision operator is processed in the current transaction time, the idle time can be fully utilized, glitch time delay in the transaction process is reduced, and the performance and time delay penetration stability of a transaction system are improved.

The invention relates to a distributed light path tracking method and system based on precomputation, and the method comprises the following steps: S1, dividing scene data, and then carrying out distributed storage, dividing the scene data into a plurality of data blocks containing a BVH structure and geometric data according to the spatial distribution characteristics and storage overhead of a scene object, the static data are distributed to the distributed storage unit in a balanced mode to serve as initial static data of the distributed storage unit; s2, generating a pre-rendering camera according to the data access frequency of the KD tree; s3, predicting the data access frequency; s4, reordering the data items according to the data access frequency; and S5, performing distributed rendering.