208 results about "Precomputation" patented technology

Fast, scalable methods and devices are provided for layer four switching in a router as might be found in the Internet. In a first method, a grid of tries, which are binary branching trees, is constructed from the set of routing filters. The grid includes a dest-trie and a number of source tries. To avoid memory blowup, each filter is stored in exactly one trie. The tries are traversed to find the lowest cost routing. Switch pointers are used to improve the search cost. In an extension of this method, hash tables may be constructed that point to grid-of-tries structures. The hash tables may be used to handle combinations of port fields and protocol fields. Another method is based on hashing, in which searches for lowest cost matching filters take place in bit length tuple space. Rectangle searching with precomputation and markers are used to eliminate a whole column of tuple space when a match occurs, and to eliminate the rest of a row when no match is found. Various optimizations of these methods are also provided. A router incorporating memory and processors implementing these methods is capable of rapid, selective switching of data packets on various types of networks, and is particularly suited to switching on Internet Protocol networks.

The present invention is directed to systems and methods for all-frequency relighting by representing low frequencies of lighting with spherical harmonics and approximate the residual high-frequency energy with point lights. One such embodiment renders low-frequencies with a precomputed radiance transfer (PRT) technique (which requires only a moderate amount of precomputation and storage), while the higher-frequencies are rendered with on-the-fly techniques such as shadow maps and shadow volumes. In addition, various embodiments are directed to a systems and methods for decomposing the lighting into harmonics and sets of point lights. Various alternative embodiments are directed to systems and methods for characterizing the types of environments for which the described decomposition is a viable technique in terms of speed (efficiency) versus quality (realism).

A fast renderer for panoramic images is herein disclosed. In an embodiment, a precomputation is made of (a) a region on a surface defined by a first transformation from a viewport to the surface and (b) a second transformation that maps from the precomputed region to the viewport. In order to render the surface on the viewport, the renderer determines what portion of the image intersects with the precomputed region and proceeds to apply the precomputed second transformation to the portion of the image, thereby resulting in a transformed image which can be rendered in the viewport for display.

A method and system for resilient routing reconfiguration, which provides provably congestion-free rerouting under a large number of failure scenarios and achieves efficiency and flexibility in accommodating different performance requirements, is disclosed. The method of embodiments comprises an offline precomputation phase and an online reconfiguration phase. Embodiments of the present invention also provide a number of useful functionalities, including (i) coping with traffic variations, (ii) supporting realistic failure scenarios, (iii) accommodating prioritized traffic with different protection levels, and (iv) balancing the trade-off between performance and resilience.

The latencies associated with cache misses or other long-latency instructions in a main thread are decreased through the use of a simultaneous helper thread. The helper thread is a speculative prefetch thread to perform a memory prefetch for the main thread. The instructions for the helper thread are dynamically incorporated into the main thread binary during post-pass operation of a compiler.

The invention discloses a big data-based online analytical processing system and method. The system can be used for carrying out quick multi-dimensional query and analysis on data sets with different scales and levels under a Hadoop environment. A query plan selected through query, planning and estimation comprises MDX query supporting Hive and Hbase precomputation cache mechanism-based multi-dimensional query. According to the system and method, optimization of the MDX query supporting Hive data warehouses on extensible cluster nodes and of the Hbase precomputation cache mechanism-based multi-dimensional query are realized, the low-delay multi-dimensional query requirements of the data sets with different scales and levels are satisfied, and the OLAP multi-dimensional query of different OLAP data organization models under a single data source background is solved. Aiming at the performance optimization problem of Hive multi-dimensional query on large-scale data sets, an Hbase cache-based segmented layered dimensionality-reduction aggregation algorithm is proposed, and the algorithm brings MOLAP for solving the multi-dimensional query calculation of large-scale data into a big data OLAP system, so that the extendibility and effectiveness of the multi-dimensional query of data with different scales and levels under a big data background are greatly enhanced.

A method and apparatus are disclosed for improving the processing time of reduced complexity sequence estimation techniques, such as reduced state sequence estimation. Precomputing the branch metrics for all possible symbol combinations in the channel memory makes it possible to remove the branch metrics unit and decision-feedback unit from the feedback loop, thereby reducing the critical path. A set of multiplexers select the appropriate branch metrics based on the survivor symbols in the corresponding survivor path cells. The computational load of the precomputations is reduced for multi-dimensional trellis codes by precomputing each dimension of the multi-dimensional trellis code separately. A hybrid survivor memory architecture is also disclosed for a RSSE for a channel having a channel memory of length L, where the survivors corresponding to the L past decoding cycles are stored in a register exchange architecture (REA), and survivors corresponding to later decoding cycles are stored in a trace-back architecture (TBA) or REA.

The present invention relates to a new parallel interference cancellation (PIC) configuration where the PIC is implemented after the rake reception and multipath combining. In the invention disclosed, the regenerated interference contributions (functions of signature sequence cross-correlations) for multiuser detection (MUD) in a multipath radio channel are explicitly filtered through the estimated multipath channels, and stored. These stored quantities already contain the effect of the channel, and only need updating according to the rate of change of channel dynamics, and not the symbol period. During each symbol period, interference is computed from each interfering user to each desired user using current estimates of symbol decisions and the aforementioned interference contributions. The precomputation of the interference contributions, which are valid for a sequence of symbols, allows for extremely low complexity baseband processing in the receiver.

A method and apparatus for selecting a subset of advertisements complying with an advertisement request from a set of advertisements is disclosed. Advertisements rules are specified according to a logical semantic simplifying search combinatorials yet allowing for flexible specification of advertising rules, and permitting significant precomputation of advertising rules to permit rapid identification of advertisements complying with advertisement requests. In one embodiment, advertisement rules and requests are represented as easily manipulable and computable bit arrays.

A pre-computation and dual-pass modular operation approach to implement encryption protocols efficiently in electronic integrated circuits is disclosed. An encrypted electronic message is received and another electronic message generated based on the encryption protocol. Two passes of Montgomery's method are used for a modular operation that is associated with the encryption protocol along with pre-computation of a constant based on a modulus. The modular operation may be a modular multiplication or a modular exponentiation. Modular arithmetic may be performed using the residue number system (RNS) and two RNS bases with conversions between the two RNS bases. A minimal number of register files are used for the computations along with an array of multiplier circuits and an array of modular reduction circuits. The approach described allows for high throughput for large encryption keys with a relatively small number of logical gates.

Embodiments of the invention provide systems and methods for automatically parallelizing loops with non-speculative pipelined execution of chunks of iterations with pre-computation of selected values. Non-DOALL loops are identified and divided the loops into chunks. The chunks are assigned to separate logical threads, which may be further assigned to hardware threads. As a thread performs its runtime computations, subsequent threads attempt to pre-compute their respective chunks of the loop. These pre-computations may result in a set of assumed initial values and pre-computed final variable values associated with each chunk. As subsequent pre-computed chunks are reached at runtime, those assumed initial values can be verified to determine whether to proceed with runtime computation of the chunk or to avoid runtime execution and instead use the pre-computed final variable values.

A secondary Booth-code-based large number multiplier belongs to the integrated circuit design technology field of the public key encryption algorithm. The present invention uses the linear transformation formula B=8a+b to do a secondary coding to the Booth 64 algorithm results generated by the partial product. The multiplier based on the secondary Booth 64code is divided into 3-level pipelining architectures. The first level architecture precomputes the multiplicands of three times with a carry look-ahead adder and at the same time does secondary Booth coding to aj with a weight of 81 and bj with a weight of 80. The second level architecture, consisting of two identical partial products selection and compression arrays, simplifies the partial products of aj and bi respectively. The third level architecture adds the partial products of the second level by an adder. The present invention improves the multiplication rate performance and can be applied to high performance RSA and ECC chips as well as large scale PKI system of servers.

A fast, texture morphing algorithm for real-time computer simulation and video games dynamically generates objects “on the fly” by simplifying and reducing the computational load required for a texture morphing/blending process. Incremental interpolation techniques compute a morph parameter based on previous value and morph change rate. Precomputed initial and incremental morph parameter values for each texel component are applied during real-time morphing procedures using integer arithmetic. Approximation errors are reduced by incrementing/decrementing by an extra integer value when the number of morph iterations is a multiple of a frame counter. The frame counter avoids over-runs, and the morphing procedure is “snapped” the texel value to the precise texture target value to prevent under-runs and corresponding artifacts. Interlacing (applying interpolation to a subset of the texels each frame) significantly reduces computational load without introducing significant image artifacts. The morph texture buffer data structure is initially decomposed off-line to reduce the number of real-time calculations required to manipulate texel component data.

Disclosed is the design and development of a new cipher called the Dragonfire Cipher. The Dragon cipher includes message authentication code and keyed random number generator. Dragonfire cipher takes this transparent method of generating S-boxes and uses them to create a cipher with keyed S-boxes. This defeats most precomputations for cryptanalysis as the S-boxes are now different between sessions.

The present invention relates to systems and methods for storing, navigating and retrieving information. In particular, the present invention is concerned with systems and methods for storing data in, for retrieving data from, and for navigating large and/or complex datasets. The systems and methods of the present invention in particular are concerned with the materialization/denormalization of complex data sets comprising a plurality of large, interconnected but distinct data record collections. The materialization/denormalization of such data sets can be performed in a precomputation phase, prior to a browsing/searching operation.

The invention relates to a multiple-input multiple-output (MIMO) signal detection method based on breadth-first tree search, mainly solving the problem of high complexity of the existing MIMO detection method. The method is implemented by the following steps: (1) preprocessing a system, wherein the step comprises QR decomposition of a channel matrix and precomputation of a path metric factor; (2)using the concept of breadth-first tree search to detect signals layer by layer: 2a) using survival paths of a previous layer to expand the paths of the current layer: using a Schnorr-Euchner enumeration method to sequentially determine path expansion sequence, expansion paths and path metrics; and 2b) using a merge sorting method to sort the path metrics of the expansion paths to determine survival paths; and (3) if the detection on all layer signals is finished, taking the survival path metric corresponding to the minimum path metric as the final detection output, otherwise, transmitting the survival path to the next layer to detect the signal of the next layer. The method of the invention has the advantages of low complexity and small performance loss, and can be applied to signal detection of an MIMO receiver of a next-generation broadband wireless communication system.

Disclosed are selected embodiments of a processor that may include a plurality of thread units and a register file architecture to support speculative multithreading. For at least one embodiment, live-in values for a speculative thread are computed via execution of a precomputation slice and are stored in a validation buffer for later validation. A global register file holds the committed architecture state generated by a non-speculative thread. Each thread unit includes a local register file. A directory indicates, for each architectural register, which speculative thread(s) have generated a value for the architectural register. Other embodiments are also described and claimed.