Large number multiplier based on secondary Booth coding

A multiplier, coding technology, applied in the direction of instruments, electrical digital data processing, digital data processing components, etc., can solve problems such as restricting applications

Inactive Publication Date: 2008-02-13
TSINGHUA UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

It reduces the number of partial products to 1 / 6 of the original, but it needs to pre-calculate 3X, 5X..., 31X, which obviously restricts the practical application of the algorithm

Method used

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  • Large number multiplier based on secondary Booth coding
  • Large number multiplier based on secondary Booth coding
  • Large number multiplier based on secondary Booth coding

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Embodiment Construction

[0066] A notable feature of the present invention is that the high-order Booth64 encoding result is re-encoded by using the secondary encoding Booth64 linear transformation formula B=8a+b, so that the partial product no longer has a large number of odd multiplicand sets {±0 , ±1, ±2, ±3, ..., ±32}, but converted to selection from the set {±0, ±1, ±2, ±3, ±4}, which requires pre-calculation of the odd part to be multiplied The number of numbers is greatly reduced, the area of ​​the multiplier is reduced, the compression rate of the partial product is increased, and the operation speed of the large number multiplier is improved.

[0067] Another feature of the present invention is that it proposes a secondary encoding Booth64 encoder structure. Booth coding logic includes three parts, which are high-order Booth coding, secondary coding and partial product selection logic. Using the information of whether the adjacent bits of the high-order Booth 64 encoding result are equal, ac...

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Abstract

A secondary Booth-code-based large number multiplier belongs to the integrated circuit design technology field of the public key encryption algorithm. The present invention uses the linear transformation formula B=8a+b to do a secondary coding to the Booth 64 algorithm results generated by the partial product. The multiplier based on the secondary Booth 64code is divided into 3-level pipelining architectures. The first level architecture precomputes the multiplicands of three times with a carry look-ahead adder and at the same time does secondary Booth coding to aj with a weight of 81 and bj with a weight of 80. The second level architecture, consisting of two identical partial products selection and compression arrays, simplifies the partial products of aj and bi respectively. The third level architecture adds the partial products of the second level by an adder. The present invention improves the multiplication rate performance and can be applied to high performance RSA and ECC chips as well as large scale PKI system of servers.

Description

technical field [0001] The invention relates to the field of integrated circuit design of public key cryptosystem algorithms, in particular to a hardware realization of large number multiplication suitable for public key cryptographic algorithms. Background technique [0002] The rapid development of e-commerce, confidential communication and other applications put forward higher requirements for information security on the open network. Public key cryptosystems such as RSA and ECC are widely used in key transfer and digital signature. The core operations of RSA and prime number field ECC are modular multiplication operations, and in order to ensure a certain degree of security, the bit length of the RSA modulus needs to be more than 1024 bits, and the bit length of the ECC modulus also needs to be more than 233 bits. The most widely used modular multiplication algorithm is the Montgomery algorithm, and its core idea is to convert the modular multiplication operation into a...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/533
Inventor 李树国颜晓东
Owner TSINGHUA UNIV
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