172 results about "Bit array" patented technology

Some embodiments provide an optimized multi-hit caching technique that minimizes the performance impact associated with caching of long-tail content while retaining much of the efficiency and minimal overhead associated with first hit caching in determining when to cache content. The optimized multi-hit caching utilizes a modified bloom filter implementation that performs flushing and state rolling to delete indices representing stale content from a bit array used to track hit counts without affecting identification of other content that may be represented with indices overlapping with those representing the stale content. Specifically, a copy of the bit array is stored prior to flushing the bit array so as to avoid losing track of previously requested and cached content when flushing the bit arrays and the flushing is performed to remove the bit indices representing stale content from the bit array and to minimize the possibility of a false positive.

A header-to-bit conversion table is provided that includes a list of address headers for registered endpoints. Assigned to each address header within the list is a bit placement within a string of bits. As messages are received, select headers within a message are compared with the address headers within the list. Each intersection or match for headers sets a bit true within a bit array for the message corresponding to the bit assignment for the header within the header-to-bit conversion table. Such array may then be compared with bit masks for each endpoint, wherein those bits set true within the bit masks represent those headers needed to satisfy the criteria for a particular endpoint. If a match is found, the message (or portion(s) thereof) may be sent to the particular endpoint for processing.

A method and apparatus for operating a memory is presented. Information is stored in the memory based on a first time domain and information is read from the memory based on a second time domain. A cooperative relationship is maintained between a write pointer which points to memory locations, where data will be stored and a read pointer which points to memory locations, from which data will be read. A FIFO memory is presented which has memory locations and a register array is presented which stores a bit array that has bit locations. Each bit location in the bit array corresponds to a memory location in the memory. As the write pointer points to a memory location and data is stored in the memory location, a bit (e.g. flag) is set in the bit array. The Flag designates whether the data stored in the memory location is available for reading. Prior to reading information from the memory location, a test is made of the bit location that corresponds to the memory location. The bit value denotes whether the data stored in the memory location is valid data and available for reading.

Disclosed are methods and tools for rapidly aligning reads to a reference sequence. These methods and tools employ Bloom filters or similar set membership testers to perform the alignment. The reads may be short sequences of nucleic acids or other biological molecules and the reference sequences may be sequences of genomes, chromosomes, etc. The Bloom filters include a collection of hash functions, a bit array, and associated logic for applying reads to the filter. Each filter, and there may be multiple of these used in a particular application, is used to determine whether an applied read is present in a reference sequence. Each Bloom filter is associated with a single reference sequence such as the sequence of a particular chromosome. In one example, chromosomal abundance is determined by aligning reads from a sequencer to multiple chromosomes, each having an associated Bloom filter or other set membership tester.

Hooking replacement and augmented API functions is disclosed. In one embodiment, an alternative implementation of one or more API functions is hooked into the operating system through utilization of a replacement API table. The functions that have been replaced, augmented, or otherwise modified have entries in the table pointing to their new implementation. The entries for functions that have not been change continue to point to their existing implementation. A bit array is also disclosed to track desired messages, as compared to undesired messages, where each bit of the array corresponds to a type of message. The table can be variably sized, and can support nested and re-entrant calls.

Event handling in multinode data processing networks, in which data structures are shared between nodes and are subject to concurrent requests for access, is facilitated through the use of a separate small data structure (bit array or linked list) which permits an event handler to hand off the task of accessing the data structure to an event handler which is already accessing data from the same data structure. This eliminates the need for locking arrangements and/or the use of special coordinating event handlers.

To realize a common-key block cipher process configuration with increased difficulty of key analysis and improved security. In a configuration for storing in a register an intermediate key generated by using a secret key transformation process and performing a transformation process on the register-stored data to generate a round key, a process of swapping (permuting) data segments constituting the register-stored data is executed to generate a round key. For example, four data segments are produced so that two sets of data segments having an equal number of bits are set, and a process of swapping the individual data segments is repeatedly executed to generate a plurality of different round keys. With this configuration, the bit array of each round key can be effectively permuted, and round keys with low relevance can be generated. A high-security cryptographic process with increased difficulty of key analysis can be realized.

A two dimensional bit array is maintained to keep track of the location of data records in a log file that is organized as a plurality of log segments, each comprising a plurality of data records. The data records are indexed in the log file according to randomized unique ids. Each column of the two dimensional bit array represents a Bloom filter corresponding to a log segment of the log file such that, given a particular randomized unique id, log segments that may contain the data record corresponding to the particular randomized unique id can be efficiently identified by utilizing Bloom filter techniques to analyze the columns of the two dimensional bit array.

Systems and methods consistent with the present invention encode a list so users of the list may make inquires to the coded list without the entire content of the list being revealed to the users. Each item in the list turns on one or more bits in the array 110. Once each item in the list has been encoded by an encoder, a bit array with high and low values is used to represent the items in the list. The bit array may be embodied in a validation system for allowing users to query the list to determine whether an inquiry item is on the list 105. The validation system determines which bits to check by executing the same coding process executed by the encoder. If all the bits are high, then the inquiry item is determined to be part of the list, if at least one of the bits is low, then the inquiry item is determined not to be part of the original list. An exemplary encoder and validation system comprises a standardizer, a hashing function unit, an extraction circuit, and an offset circuit.

The present invention provides a novel operational method of twin MONOS metal bit or diffusion bit structure for high-speed application. In a first embodiment of the present invention, the alternative control gates are set at the same voltage. In a second embodiment of the present invention, all the control gates are set at the operational voltage from the beginning. In both embodiments, the bit line and word gate are used to address the selected memory cell.

A method and apparatus for selecting a subset of advertisements complying with an advertisement request from a set of advertisements is disclosed. Advertisements rules are specified according to a logical semantic simplifying search combinatorials yet allowing for flexible specification of advertising rules, and permitting significant precomputation of advertising rules to permit rapid identification of advertisements complying with advertisement requests. In one embodiment, advertisement rules and requests are represented as easily manipulable and computable bit arrays.

The optimized inequality join method is a method for joining relational tables on input inequality conditions. The optimized inequality join method is a relatively fast inequality join method using permutation arrays to store positional information for sorted attributed values. Additionally, space efficient bit arrays are used to enable optimization, such as Bloom filter indices, thus providing faster computation of the join results. The method may be used, for example, for joining various inequalities associated with a variety of measured environmental conditions for raising an alarm when certain conditions are met.

Some embodiments provide an optimized multi-hit caching technique that minimizes the performance impact associated with caching of long-tail content while retaining much of the efficiency and minimal overhead associated with first hit caching in determining when to cache content. The optimized multi-hit caching utilizes a modified bloom filter implementation that performs flushing and state rolling to delete indices representing stale content from a bit array used to track hit counts without affecting identification of other content that may be represented with indices overlapping with those representing the stale content. Specifically, a copy of the bit array is stored prior to flushing the bit array so as to avoid losing track of previously requested and cached content when flushing the bit arrays and the flushing is performed to remove the bit indices representing stale content from the bit array and to minimize the possibility of a false positive.

A buffer having an associated state array to store the current state of the buffer. The state array includes a bit array having a number of entries, each of the entries including a status bit to indicate storage of a corresponding packet in the buffer.

The embodiment of the invention discloses a processing method and device based on a block chain system. The method comprises the following steps: when a node executes a transaction in a to-be-consensus block, generating a plurality of pieces of state data corresponding to the transaction, constructing a Bloom filter corresponding to the block by using the plurality of pieces of state data, and updating a block head of the block by using a hash value of the Bloom filter corresponding to the block; thus, after the node determines that the block consensus succeeds, the block header of the block being linked, and using the Bloom filter corresponding to the block and the multiple pieces of state data for updating the preset database of the node. According to the embodiment of the invention, compared with a data structure of a Merkle tree, the Bloom filter can use a common bit array to store a plurality of pieces of state data, so that the storage space can be well saved and the query response speed can be improved by using the Bloom filter to store the state data corresponding to the transaction, thereby reducing the calculation overhead and cost of the blockchain system.

The invention discloses a vulnerability scanning method and server and a risk assessment system and relates to the technical field of information security. The method comprises the steps that the server receives a scanning parameter configuration file from a client side and scans a scanned target according to the scanning parameter configuration file; the server extracts keywords from a scanning result; based on a bloom filter algorithm, the server performs quick matching on the extracted keywords and vulnerability features, compressed based on the bloom filter algorithm, in a vulnerability library, and the server determines whether vulnerability exists in the scanning result according to a matching result. As the vulnerability features are compressed based on the bloom filter algorithm, the know vulnerability features can be compressed into an m-bit array, and then storage space is reduced. In addition, a Hash operation is performed on the scanned keywords based on the bloom filter algorithm, matching is performed on Hash operation results and the m-bit array of the known vulnerability features, in this way, it can be determined whether the vulnerability exists in the scanning result, and the matching speed is higher.

An apparatus, system, and method are disclosed for logging operations for a database. An operation event module detects an operation on a record in a database table. A translation module creates a changed field bit field, one or more operation time bit fields, and a user bit field. The translation module creates the changed field bit field by encoding indicators of one or more fields of the record that the operation is configured to change, creates the one or more operation time bit fields by encoding time information for the operation, and creates the user bit field by encoding information of a user associated with the operation. A consolidation module packs at least the changed field bit field, the one or more operation time bit fields, and the user bit field into a single bit array. A log module stores the bit array in a change log.

An encoding method and apparatus and a decoding method and apparatus are provided. The encoding method includes encoding data, generating a data bit array comprising the encoded data and encoding information, and generating an align bit array comprising one or more Is. According to the encoding method and apparatus and the decoding method and apparatus, it is possible to enhance the quality of decoded data by inserting various information into an align bit array that is included in a bitstream for aligning a plurality of encoded data bit arrays with one another. In addition, according to the encoding method and apparatus and the decoding method and apparatus, it is possible to efficiently utilize data bandwidths that are allocated for the encoding/decoding of data at low bitrates by enhancing the efficiency of data encoding.

In a data cache unit that exchanges data signal groups with at least two execution units, the operation of the data cache unit is implemented as a three-stage pipeline in order to access data at the speed of the system clock. The data cache unit has a plurality of storage cell banks. Each storage cell bank has valid bit array unit and a tag unit for each execution unit incorporated therein. Each valid bit array unit has a valid/invalid storage cell associated with each data group stored in the storage cell bank. The valid bit array units have a read/write address port and snoop address port. During a read operation, the associated valid/invalid signal is retrieved to determine whether the data signal group should be processed by the associated execution unit. In a write operation, a valid bit is set in the valid/invalid bit location(s) associated with the storage of a data signal group (or groups) during memory access. The valid bit array unit responds to a snoop address and a control signal from the tag unit to set an invalid bit in a valid/invalid bit address location associated with the snoop address. The tag unit can be divided into a plurality of tag subunits to expedite processing.

A programmable logic block in an integrated circuit comprising a plurality of macrocells, an AND-array, an OR-array, and a logic circuit. The plurality of macrocells may comprise logic that may be configured to (i) generate and propagate an inverted carry-input signal and (ii) generate a sum bit. The AND-array may comprise at least two product terms per macrocell. The OR-array may be configured to generate a sum-of-products term for each macrocell in response to the two product terms. The logic circuit may be configured to (a) receive (i) the product terms and (ii) the carry-input signal generated by a first macrocell of the plurality of macrocells and (b) generate (i) a block carry-propagate signal, (ii) a block carry-generate signal, and (iii) a block carry-output signal.

The invention provides an authentication certificate generation method based on a block chain. The method comprises the following steps: (1) performing, by an certificate authentication center node, hash mapping on a received request to obtain bit arrays, sending the bit arrays to other certificate authentication center nodes, and performing, by each node, 2/3 intersection operation on all received bit arrays; (2) randomly selecting a block building node according to a polling scheduling algorithm, constructing a block by using request data corresponding to a common intersection, and broadcasting the block to the other nodes; (3) verifying, by each node, the newly built block, then signing a verification result with an own private key, and broadcasting the verification result to the othernodes; (4) performing, by each node,verification and calculation on the received verification result to obtain a voting set, then signing the voting set and broadcasting the voting set to the other nodes; and (5) performing, by each node,verification and summarization on the received voting sets of the other nodes, and determining whether to add the block to the block chain after the consensus operation. By using the method of the invention, multiple nodes perform mutual verification, so that the robustness of the system can be improved, and when a certain node is attacked, the consistency andintegrity of certificate generation are not affected.

The invention relates to a method for improving error correction capacity and a related memory device and a controller of the memory device. The method comprises the following steps of: respectively calculating a plurality of first parity check codes aiming at a plurality of lines of a data bit array; respectively calculating a plurality of second parity check codes aiming at a plurality of groups formed by a plurality of rows of the data bit array, wherein each of the groups comprises two or more of the rows, and the groups are not overlapped; and performing encoding/decoding corresponding to the first and second parity check codes. The invention also provides a related memory device and a controller of the memory device. In the invention, the error correction capacity of the controller of the memory device can be improved without increasing error correction code engine encoding/decoding digit, and the remaining storage space can be properly utilized by the realized error correction without causing waste. Therefore, the aim of giving consideration to operation efficiency and system resource use control and management can be fulfilled under the conditions of not increasing the chip area and related cost.