93 results about "Bit array" patented technology

The invention relates to the technical field of equipment fault prediction, in particular to a cup labeling equipment fault prediction method and system based on machine learning. According to the method, equipment operation state parameters are converted into a multi-mode pulse sequence with a timestamp synchronization characteristic; loading the purified pulse flow to a quantum bit array for entanglement state evolution, and extracting a three-mode entanglement association tensor; carrying out dimensionality reduction projection on the three-mode correlation tensor to an equipment degradation manifold space, and determining quantum tunneling probability density distribution; constructing a time-varying Hamiltonian of an equipment degradation state based on quantum tunneling probability density distribution, and generating a degradation track cluster according to the time-varying Hamiltonian; and performing time sequence convolution processing on the degradation track cluster, performing probability amplitude amplification on a fault critical point in the track cluster by using an energy level splitting characteristic of a time-varying Hamiltonian, and generating a space-time probability cloud picture. The fault evolution law can be visually presented, the accuracy and timeliness of early fault early warning are improved, and a reliable basis is provided for predictive maintenance.

A programmable driver circuit (54) and related method (600) for simultaneously controlling multiple tunable probabilistic bit generators are disclosed. The driver circuit comprises a plurality of programmable voltage generators (52; 30), a programming unit (35) and a non-volatile memory unit (34a-b). Input terminals of the plurality of programmable voltage generators are jointly connectible to a single voltage supply source. The programming unit is configured to generate a sequence of programming pulses for the different voltage generators. Each voltage generator comprises a single-stage or multi-stage voltage divider circuit (31) formed by a series of resistive elements (32-1; 32-2; 33). The non-volatile memory unit (34a-b) comprises at least the resistive element positioned first in the series of resistive elements as a programmable resistance and a program control transistor (34-1) connected in series between the programmable resistance and a fixed reference voltage. A control gate of the program control transistor is operatively coupled to the programming unit to receive the sequence of programming pulses for the programmable voltage generator when operated in a programming mode.

The invention relates to the field of safety practical training, in particular to an engineering construction safety practical training method and system based on big data, and the method comprises the steps: determining a preset analysis condition corresponding to a target person according to a frame selection duration characterization value and a frame selection duration fluctuation value when the answering frequency of the target person is equal to the optimization response frequency; under a first preset analysis condition, determining a compensation mode as point location array compensation or frame parameter compensation according to a point location aggregation similarity value and a point location aggregation representation value corresponding to the test question point location distribution diagram of the target person; when frame parameter compensation is carried out, a frame parameter compensation strategy is determined according to the number proportion of the first anchoring frames and the second anchoring frames, and compensation is carried out based on frame neighborhood parameters or frame areas; under a second preset analysis condition, increasing and adjusting the number of optimization response times; the test questions are dynamically adjusted to improve the safety training efficiency.

The embodiment of the invention provides a distributed data deduplication method and product. The method comprises the steps of obtaining a data key of data to be subjected to deduplication; distributing the data to be subjected to duplicate removal to the ith sub-bucket according to the mixed hash value of the data key; mapping the mixed hash value according to a hash function attribute value configured for the ith sub-bucket to obtain k position numbers; reading numerical values of positions corresponding to the k position numbers from a bit array which is stored at the current moment and corresponds to the ith sub-bucket to obtain k numbers; if it is confirmed that the k numbers are all first numerical values, it is confirmed that the data to be subjected to duplicate removal belong to duplicate data; and if at least one of the k digits is confirmed to be a second numerical value, confirming that the data to be subjected to duplicate removal belongs to new data. According to the embodiment of the invention, the speed and accuracy of big data deduplication processing are remarkably improved, and the problem of single-node calculation overload (different buckets can be distributed to different calculation nodes) is effectively solved.

The invention relates to the field of radio frequency power control, and discloses a radio frequency power control method and system for a 5G mainboard, and the method comprises the steps: 1, capturing the phase fluctuation of a millimeter wave frequency band through employing a superconductive quantum bit array, building a virtual channel response based on quantum entanglement state measurement, generating a channel topological graph, calculating and predicting a channel state based on the channel topological graph, and carrying out the calculation of a predicted channel state; calculating a prediction error according to the measured actual channel state, and adjusting the radio frequency power; 2, fusing the quantum measurement matrix and the deep residual network, introducing a residual attention mechanism to reconstruct an abnormal channel, carrying out local optimization, solving asymmetric Nash equilibrium, reducing algorithm complexity and calculation complexity, dynamically controlling radio frequency power, suppressing interference and improving power amplifier performance; and step 3, analyzing the influence of environmental factors on system errors, jointly calibrating and correcting the errors, constructing a learning model and expanding a dynamic range, determining the actual maximum transmitting power and distributing radio frequency power.

Qubit arrays having substrates that are engineered to suppress correlated dephasing errors, correlated relaxation errors, or both are provided. Also provided are quantum circuits incorporating the qubit arrays and quantum computers incorporating the quantum circuits. The engineered substrates can be used to suppress noise and correlated errors in any qubit array that suffers from charge fluctuations or other noise that creates a non-equilibrium, error-producing state in the qubit array.

An apparatus may include a transmitter and one or more processors configured to identify a code rate of a low-density parity-check (LDPC) code, receive, by an LDPC encoder, a set of information bits and encode, using the code rate, the set of information bits to generate a set of encoded bits and a set of parity bits, generate, from the set of encoded bits, a matrix of bit arrays, discard one or more parity bits from the set of parity bits to generate a parity bit array with a size equal to a number of column of the matrix, generate a bit array by concatenating (1) one or more bit arrays selected from the matrix of bit arrays and (2) one or more bits selected from the parity bit array corresponding to the one or more bit arrays, and modulate, by a modulator, the bit array to generate modulated data.

The invention discloses clock gating of an idle index flip-flop array, and specifically describes a system comprising: a first storage element having a plurality of data storage locations; a second storage element having a bit array indicating availability of a corresponding data storage location of the plurality of data storage locations; and a control circuit. The control circuit may include at least a first switching element coupled to a first set of bits in the bit array and at least a second switching element coupled to a second set of bits in the bit array, the at least first switching element selectively enabling the first set of bits to be read or written in response to activation by a first clock gating signal; the at least second switching element selectively enables a second set of bits to be read or written in response to activation by a second clock gating signal.

The invention discloses a duplicated data detection method and device, a storage medium and a computer program product, and relates to the technical field of data processing, a preset bit array is constructed through a plurality of preset functions and stored data blocks to serve as the basis of data duplicated detection of to-be-detected data blocks, and the data duplicated detection efficiency is improved. The to-be-detected data blocks which may be repeated are preliminarily screened out through the preset bit array, and then the to-be-detected data blocks which may be repeated are further subjected to refined detection through the preset hash table, so that layered detection of data is realized, and compared with hash table look-up traversal comparison of all the to-be-detected data blocks, the detection efficiency is effectively improved, and the detection time is shortened. And meanwhile, the detection accuracy is ensured.

The present invention addresses the problem of providing: a high-speed Coulomb blockade thermometer that can reduce the effects of self-heating and achieve a high S / N; and a quantum computer that uses the Coulomb blockade thermometer.　A preferred embodiment of the present invention is a quantum computer that comprises a quantum bit array chip that forms semiconductor quantum dots, a cooling device that cools the quantum bit array chip, a Coulomb blockade thermometer that is provided inside the cooling device, a temperature control unit that controls a heat source that is inside the cooling device, and a storage unit that stores a conversion table for converting the conductance of the Coulomb blockade thermometer to temperature. The temperature control unit applies a constant voltage to the Coulomb blockade thermometer to measure the conductance, references the conversion table to convert the measured conductance to temperature information, and controls the heat source on the basis of the temperature information.

The present invention discloses a compression index and query method for an attribute graph, which is applied to an attribute graph database system. The attribute graph maintained by the attribute graph database system includes a plurality of vertices, edges, and their corresponding attributes. The method includes: constructing an adjacency list for each vertex according to the attribute graph; constructing a compressed structure of the graph structure according to the adjacency list of each vertex; calculating vertex / edge numbers according to the compressed structure of the graph structure, obtaining the location of the attribute in the attribute compression index according to the vertex / edge numbers and the corresponding bit arrays, and extracting the attribute values from the attribute compression index; the attribute compression index includes a vertex attribute compression index and an edge attribute compression index; the bit arrays correspondingly record the starting positions of all edge attributes / vertex attributes; querying the attribute graph according to the compressed structure of the graph structure and the attribute compression index. The method of the present invention improves the query efficiency of the attribute graph database and reduces the storage space.

The invention provides a security detection method and device, electronic equipment, a storage medium and a program product, and relates to the technical field of cloud security, and the method comprises the steps: firstly, obtaining a security detection rule and a to-be-detected sample; then, performing security detection on a to-be-detected sample by using a security detection rule; wherein the security detection rule is stored based on a bit array and a hash function. In the embodiment, the client stores the security detection rule based on the bit array and the hash function, so that the storage space can be reduced; moreover, the security detection is carried out on the to-be-detected sample by using the security detection rule stored based on the bit array and the hash function, so that the security detection speed can be improved, and the resource occupation of the client to the terminal equipment is reduced.

The invention discloses a method for improving the precision of an MCU for controlling a crystal oscillator, and relates to the technical field of microcontrollers. Setting a DAC output precision improvement multiple N, and calculating a register configuration range after improvement; calculating a theoretical register configuration value of a voltage needing to be output after the output precision of the DAC is improved; rounding off the calculated theoretical register configuration value to obtain an actual configuration value; creating an N-bit array for storing an actual DAC register value, dividing an actual configuration value by a lifting multiple N, rounding down, and assigning all elements in the array to obtain a rounding down result; calculating a result k obtained by taking a remainder from the lifting multiple N by an actual configuration value, adding 1 to the first k number in the array and then randomly disorganizing; creating timer interruption, and writing an array value into a DAC register every 1 / N seconds; and after all the data are written in, the DAC module outputs a voltage effective value with the control precision improved by N times within one second. According to the invention, high-precision voltage output of the voltage-controlled pin of the crystal oscillator is realized under the condition that hardware configuration is not changed.

This application discloses a capacitor mismatch testing method, comprising: measuring the actual full-rail amplitude of an analog-to-digital converter (ADC) included in a radio frequency transceiver circuit; determining, based on the actual full-rail amplitude, a mismatch test signal corresponding to each capacitor in an N-bit array of capacitors included in the ADC; performing a test using the mismatch test signal corresponding to each capacitor to obtain a test result corresponding to each capacitor; wherein the test result indicates whether each capacitor is mismatched. This application also discloses a capacitor mismatch testing apparatus, device, storage medium, and computer program product.

Data characterizing a request to access a database record, a data attribute of the database record, and an authorization token are received. Based on the received data, permission to access the database record is determined by at least validating the authorization token using the data attribute. The authorization token can be generated by producing hash values for the database record and generating a bit array for the hash values. Related apparatus, systems, techniques, and articles are also described.

A technique for remapping pending bit array read requests includes a computing device including a plurality of data storage devices, a request manager, and a remapping manager. The request manager is used to receive a request to read PBA data from a main PBA mapped to a plurality of sub-pending bit arrays (PBAs). Each sub-PBA is associated with a different data storage device in the data storage device. The request includes attribute data indicating an address in the main PBA from which the PBA data is to be read. The remapping manager is used to determine one or more bit addresses from the attribute data, compare the one or more bit addresses with the addresses of the sub-PBAs in the main PBA to determine a set of sub-PBAs to be read, and map the one or more bit addresses to the determined set of sub-PBAs to be read.

Data characterizing a request to access a database record, a data attribute of the database record, and an authorization token are received. Based on the received data, permission to access the database record is determined by at least validating the authorization token using the data attribute. The authorization token can be generated by producing hash values for the database record and generating a bit array for the hash values. Related apparatus, systems, techniques, and articles are also described.

A computer-readable recording medium stores a program for causing a computer to execute a process including: generating an integer array of types as an initial point of each training data of the training data group; searching for the first point by providing a constraint in which, when the first point is retrieved, an index of a variable in the integer array is set to i and an index that represents a type of the variable is set to j for each training data, a case of i=j in the integer array in a matrix of i and j is set to 1 and another case is set to 0 to perform conversion into a bit array of i and j, and variable in each row is 1 in the matrix; and applying the genetic algorithm to a format of the integer array when the second point is retrieved.

A distributable hash filter for achieving non-probabilistic set inclusion is provided. In some embodiments, a method includes recursively executing a procedure comprising: updating a bit array using a set of allowed object identifiers and a hash function; further updating the bit array using a set of disallowed object identifiers and the hash function; upon a collision, repeating the procedure with a new allowed set and a new hash function that includes object identifiers from the original allowed set that collide with the disallowed set until a round is reached where no collisions occur; generating a data structure comprising the bit array created during each recursive round; and compressing the data structure.

This invention provides an automated testing method and system for segment LCD screens. The method includes: establishing a data path between a test platform and the device under test (DUT), wherein the data path establishment strategy is adaptively selected based on the architecture of the DUT; pre-establishing a video memory mapping configuration file and test cases, and loading them onto the test platform; establishing a frame synchronization mechanism when the test platform receives video memory data from the DUT; detecting whether the DUT has physical faults or electrical connection anomalies, and generating physical test results; translating the segment codes of the test cases into bit arrays based on the video memory mapping configuration file, and comparing them with the actual arrays obtained by parsing the actually received video memory data; and generating a corresponding diagnostic report based on the comparison results and the physical test results.

Methods, network devices and computer readable media are disclosed relating to a communication network. In one embodiment, a method includes receiving a message comprising a message bit array. The message bit array identifies egress nodes for the message within a bit indexed explicit replication (BIER) domain of a communications network. A first bit position in the message bit array represents a first one or more of the egress nodes, and a bit value at the first bit position indicates that the message is to be forwarded to one of the first one or more of the egress nodes. The method further includes accessing a first forwarding table entry corresponding to the first bit position, determining whether the first bit position is an anycast bit position having multiple corresponding forwarding table entries, and forwarding the message to one of the first one or more of the egress nodes.

The present application discloses a method and apparatus for data processing, a computer device, and a storage medium. The present application can be applied to various scenarios such as cloud technology, artificial intelligence, intelligent transportation, and assisted driving, including: obtaining a set of data to be processed; creating an initial bit array set based on the set of data to be processed; processing each piece of data to be processed in the data to be processed based on the initial bit array set to obtain the modulo values corresponding to each piece of data to be processed in each initial bit array; replacing the position parameters of each initial digit in N initial bit arrays with the modulo values corresponding to each piece of data to be processed in each initial bit array to obtain a target bit array set; and determining target data from L pieces of data to be processed based on the target bit array set. Through the above method, it is not necessary to access external storage for each piece of data, and the consumption of storage resources can be reduced in scenarios with a large amount of data, thereby improving the real-time data processing efficiency.

The present application provides a logical plan generation method and a database system, which can be applied to the technical field of computers. The method comprises: acquiring a bit array of a source table, computing an operation data volume of the source table on the basis of the bit array, and generating a logical plan on the basis of the operation data volume, wherein the operation data volume is a data volume, satisfying a screening condition, in the source table. Because the operation data volume can more accurately reflect the actual system resource requirements for executing a database operation, the logical plan generation method provided by the present application can generate a logical plan which is more rational and can better reflect actual requirements, so that when a physical plan corresponding to the logical plan is subsequently generated, the rationality of the physical plan is correspondingly improved, which is equivalent to improving the execution efficiency of user requests.

An in-memory computation (IMC) circuit. The IMC circuit includes: an array comprising a matrix of memory cells having a plurality of rows and columns, wherein memory cells within the same column are connected through a common bit line and memory cells within the same row are connected through a common word line, wherein the memory cells are configured for storing weights of a trained neural network architecture, wherein the order of the weights is pre-scrambled; at least one decoder configured for outputting a number of shifting operations to be performed by each shifting register of a plurality of shifting registers using a secret key; the plurality of shifting registers configured for shifting outputs of the array according to the output of the decoder.

Techniques for data compression for efficient network management are described herein. In one example, group(s) of bytes are formed from among input bytes to be compressed. The groups are formed by including bytes having at least a certain number (e.g., three) zero-valued most significant bits (MSBs). A byte of input data having several zero-valued MSBs may be in several groups. A group having the largest product (number of bytes in the group times number of zero-valued MSBs in all bytes in the group) may be selected. A compressed-bytes array may be formed with data of the selected group of bytes, wherein the number of zero-valued MSBs originally present in all of the bytes of the group of bytes has been removed (to compress the array). An uncompressed-bytes array may be formed with bytes of the input bytes of data not in the selected group of bytes. An address-bit array may be formed to indicate the array in which data associated with each of the input bytes of data is stored.

Aspects of the present disclosure involve systems, methods, for encoding a firewall ruleset into one or more bit arrays for fast determination of processing of a received communication packet by a firewall device associated with a network. Through this bitmap, a number of computation operations needed to determine a processing rule for a received packet is significantly reduced compared to the traditional approach of using a hash or a longest prefix match technique. Rather, determining a processing rule for a received packet may include determining a bit value within one or more arrays. In one implementation, a firewall rule may be encoded into a 64-bit array of bit values in which each bit of the array corresponds to a particular processing rule for a particular network address. The firewall rule may be encoded into a bitmap array of bit values by asserting a particular bit within the array.

This application discloses a data processing method, apparatus, device, and storage medium, relating to the field of computer technology. The data processing method includes: in response to the presence of sensitive data of a numeric type in the data to be processed, obtaining binary data corresponding to the sensitive data; storing the binary data bit by bit in an initial bit array to obtain a first bit array; obfuscating the first bit array according to a preset obfuscation rule to obtain a second bit array; desensitizing the second bit array to obtain an encrypted string corresponding to the sensitive data; and replacing the sensitive data in the data to be processed with the encrypted string. This application, while ensuring the protection of sensitive data, can reduce the amount of encrypted data, making it more convenient for transmission and storage.

This invention belongs to the field of communication technology, specifically relating to a method for content delivery and local confirmation for glasses in a private network environment. The method includes the following steps: Step 1: The content delivery server assigns a task identifier to each task content data and sends it to the glasses terminals within the private network via a User Datagram Protocol (UDP) broadcast channel; Step 2: Each glasses terminal receives the UDP broadcast data until it recovers the complete task content data and registers it in its local task table; Step 3: When a glasses terminal executes task content data in the registered state, it triggers a voice confirmation module to collect the wearer's confirmation-type command voice to generate a task confirmation event. The content delivery server then parses the Bloom filter digest bit array to obtain the set of completed tasks and updates the task management record. This invention significantly improves the efficiency, reliability, and controllability of task management in a private network environment.

To expand quantum bits in two dimensions using a current semiconductor manufacturing method, in a quantum information processing device.SOLUTION: A first layer has a first gate electrode row arranged in a first direction to control quantum bits of a quantum bit row, and a second gate electrode row arranged in the first direction to control quantum bit interactions of an interaction row. The second layer has a third gate electrode row arranged in a second direction, and a fourth gate electrode row arranged adjacent to the third gate electrode row in the second direction. The third gate electrode row and the fourth gate electrode row control some of the quantum bits of the multiple quantum bits and some of the multiple quantum bit interactions, respectively.SELECTED DRAWING: Figure 1

The application discloses a unified storage conversion method and system for finite element analysis result data, relates to the field of data conversion, and solves the problem that current finite element result data cannot be effectively stored and converted. The method comprises the following steps: converting different original files into identifiable files through a converter plug-in, and extracting finite element result data in the identifiable files; processing three-dimensional result arrays in the finite element result data to obtain reorganized result arrays; performing data deduplication on the finite element result data, and intelligently grouping different standard physical quantities in the reorganized result arrays according to byte bits; storing node coordinate arrays, element connectivity arrays and different byte bit arrays into different subfolders respectively, and querying the byte bit arrays according to different query conditions. The application realizes effective storage and conversion of finite element result data.