Method, System, Computer Program Product, and Data Processing Program for Verification of Logic Circuit Designs Using Dynamic Clock Gating

Abstract

A method and system for verifying a logic circuit design using dynamic clock gating is disclosed. The method comprises choosing at least one master seed to determine initial values as initialization for said logic circuit and / or stimuli data for at least one interface of said logic circuit, choosing at least two different dynamic clock gating configurations for every chosen master seed, executing a functional simulation with said logic circuit for every chosen dynamic clock gating configuration by using said determined initialization and / or stimuli data based on a corresponding master seed, comparing simulation results of functional simulations against each other executed with said logic circuit for at least two different chosen dynamic clock gating configurations, and reporting an error if said at least two simulation results are not identical.

Description

BACKGROUND[0001]1. Field[0002]The present invention relates in general to the field of verifying logic circuit designs, which are especially used in processor systems, and in particular to a method and a system for verification of logic circuit designs using dynamic clock gating, wherein the logic circuit design comprise processors, cores, units, macros and / or sub macros for example. Still more particularly, the present invention relates to a data processing program and a computer program product for verification of logic circuit designs using dynamic clock gating.[0003]2. Description of the Related Art[0004]Dynamic clock gating is one method for minimizing the power consumption of logic circuitries which are used in electronic devices. The main idea is to disable clocking of logic components that are currently not in use. Clocking is enabled again based on incoming stimuli data and / or signals to that logic component. Dynamic clock gating is a fine grained mechanism to enable and di...

AI Technical Summary

Benefits of technology

[0029]All in all, embodiments of the present invention disclosed herein are able to verify the design goal for logic circuit designs using dynamic clock gating to behave completely independent on the dynamic clock gating configuration. So embodiments of the present invention do guarantee functional correctness of the logic circuit design and are able to detect any changes in the behavior of the logic circuit design based on the dynamic clock gating configuration that could result in serious performance degradations.

[0032]Embodiments of the present invention decrease the error probability in the logic circuit design and lower the risk of design failures in the field for applications that require a high reliability and a high availability and a good power management.

Problems solved by technology

However, dynamic clock gating adds additional complexity to the logic circuit design which has to behave completely independent on the dynamic clock gating configuration.

This approach relies on interface signals and / or data only and, for example, does not check performance behavior of the logic circuit design that is not described by the interface specification.

The described state of the art functional verification methods can not verify the design goal for logic circuit designs using dynamic clock gating to behave completely independent on the dynamic clock gating configuration.

The state of the art verification methods only guarantee functional correctness of the logic circuit design and are not able to detect any changes in the behavior of the logic circuit design based on the dynamic clock gating configuration that could result in serious performance degradations.

Due to a clock gating problem the behavior of the LRU-Algorithm can be changed in a problematic way.

For example, in our case the behavior changed in a way that the cache behaved as a two way associative cache only, resulting in a significant reduction in system performance.

Another example of problems which could arise in a logic circuit design due to dynamic clock gating is an arbiter.

Any difference in the results of the at least two simulation runs for the different clock gating configurations is considered to be an error.

Obviously, no exhaustive testing is possible in a reasonable amount of time.

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