Circuit safety DFT (design for testability) method for accelerating hardware Trojan trigger and hardware Trojan detection method

A hardware Trojan and design method technology, applied in electronic circuit testing and other directions, can solve problems such as difficult detection, and achieve the effect of speeding up the triggering speed

Active Publication Date: 2015-09-30
58TH RES INST OF CETC
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Problems solved by technology

[0004] The above two types of methods can detect a certain type of specific hardware Trojan to a certain extent, but both rely on the need to trigger the hardware Trojan or require the hardware Trojan to be in a working state all the time, which

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  • Circuit safety DFT (design for testability) method for accelerating hardware Trojan trigger and hardware Trojan detection method
  • Circuit safety DFT (design for testability) method for accelerating hardware Trojan trigger and hardware Trojan detection method

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Embodiment Construction

[0023] The present invention will be further described below in conjunction with specific drawings and embodiments.

[0024] Design for Testability (DFT, Design for Testability) is a very important part of integrated circuit design. It is mainly used to detect whether there are manufacturing defects in the chip during the manufacturing process, which affects the function of the circuit and the yield. And people have developed a variety of DFT techniques to more effectively detect defects in chip manufacturing.

[0025] However, for the security detection of whether there is a hardware Trojan in the integrated circuit, there is no general and standard process such as DFT at present.

[0026] The current technology for hardware Trojan detection, such as logic testing, requires the hardware Trojan inside the circuit to trigger and change the logic value of the internal nodes of the circuit, so that it can be judged whether there is a hardware Trojan inside the circuit by observin...

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Abstract

The invention relates to a circuit safety DFT (design for testability) method for accelerating hardware Trojan trigger. The method comprises the following steps: firstly, function design and verification of a circuit are finished; secondly, clock frequency higher than that during normal operation is selected and taken as the clock frequency of a safe test mode; then work including corresponding synthesis, scan chain insertion, placing and routing, static timing analysis and the like is finished, and exactly correct functions and timing sequences for function test and scan chain test under the clock frequency of the safe test mode are guaranteed. Therefore, after the circuit is manufactured, the circuit is configured with the safety test mode with high clock frequency, and for hardware Trojans such as time bomb type hardware Trojans having a time-dependent trigger condition, the hardware Trojan trigger probability can be accelerated remarkably when the circuit designed with the method is used. The design method can further increase the hardware Trojan implantation difficulty.

Description

technical field [0001] The invention relates to a circuit security testability design method capable of accelerating the triggering of hardware Trojan horses, especially a design method and detection process that make hardware Trojan horses easier to trigger by adding additional circuits in the circuit design stage, especially suitable for detection needs A hardware Trojan that takes a long time to trigger. Background technique [0002] With the development of the integrated circuit industry towards global cooperation, more and more third parties are involved in the integrated circuit industry chain, which makes more and more uncontrolled factors in the design and manufacturing process of integrated circuits. This raises concerns about the security of integrated circuits. Due to the participation of third-party uncontrolled links, integrated circuits are easily modified maliciously and implanted into hardware Trojan horses during the design and manufacturing process. Some ...

Claims

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Application Information

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IPC IPC(8): G01R31/28
Inventor 周昱王淑芬
Owner 58TH RES INST OF CETC
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