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Method for generating RTL hardware Trojan test vectors

A technology of test vectors and hardware Trojan horses, applied in the direction of measuring electricity, measuring devices, measuring electrical variables, etc., can solve problems such as difficulty in achieving consistency, achieve the effects of improving overall efficiency, speeding up speed and effectiveness, and improving branch coverage

Active Publication Date: 2017-11-21
NORTHWESTERN POLYTECHNICAL UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This method does not directly analyze the verilog code, and it is difficult to be completely consistent with the original verilog design by means of code conversion.

Method used

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  • Method for generating RTL hardware Trojan test vectors
  • Method for generating RTL hardware Trojan test vectors
  • Method for generating RTL hardware Trojan test vectors

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0065] Select RS232-T400 on Trust-Hub as the analysis object, which contains three verilog files: uart.v, u_xmit.v, u_rec.v. The three verilog files are shown below. The Trojan trigger in the top-level file uart.v compares the sent and received data, and when both are equal to 8’h4c, the Trojan is activated. The payload part of the Trojan will replace 4 bits in the received data.

[0066] 1.uart.v program source code:

[0067]

[0068]

[0069]

[0070] 2.u_xmit.v program source code:

[0071]

[0072]

[0073]

[0074] 3.u_rec.v program source code:

[0075]

[0076]

[0077]

[0078] This embodiment takes uart.v as an example, which contains 2 instantiated statements, and u_xmit.v and u_rec.v will be analyzed in sequence.

[0079] Step 1: Generation of control flow graph

[0080] 1) Deeply traverse the syntax parse tree (parseTree) of the uart.v file to obtain the information of the statement nodes. For example: the first node of the entire fil...

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Abstract

The invention discloses a method for generating RTL hardware Trojan test vectors. The method mainly includes generation of a control flow chart, concurrent symbol execution, and satisfiability solving and generation of test vectors. The method provided by the invention adopts a method of statically analyzing Veri log codes, and adopts a multi-thread concurrency technology to realize concurrent symbol execution of the Veri log codes, thereby achieving the purpose of rapidly generating test vectors with a high path coverage rate.

Description

technical field [0001] The invention relates to the field of integrated circuit testing, in particular to a method for generating RTL hardware Trojan test vectors, which can quickly generate a test with high path coverage and an activatable condition-triggered hardware Trojan according to the characteristics of a condition-triggered hardware Trojan vector. Background technique [0002] In the design of digital integrated circuits, different design links correspond to the design of different abstract levels. The levels of abstraction, from high to low, are functional specification, algorithm level / microarchitecture level design, register-transfer level design (register-transfer level, RTL), gate level (gate level) design and physical level design. Hardware Trojans can be distributed on different levels of abstraction, mainly including system level, behavior description level, register transfer level, gate level, transistor level and physical level. People such as N Jacob an...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/3183G01R31/317
CPCG01R31/31719G01R31/318371
Inventor 沈利香慕德俊时翔徐强邢业新何松袁晓宇
Owner NORTHWESTERN POLYTECHNICAL UNIV
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