Design segmentation method for multiple FPGAs

A technology for configuring groups and vertices, applied in CAD circuit design, computer-aided design, calculation, etc., can solve problems such as energy-consuming and time-consuming

Active Publication Date: 2021-01-05
S2C
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Usually the entire design segmentation process needs to consider many factors and processing work, which is very energy-intensive and time-consuming

Method used

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  • Design segmentation method for multiple FPGAs
  • Design segmentation method for multiple FPGAs

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Embodiment Construction

[0020] Embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings.

[0021] Embodiments of the present disclosure are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Apparently, the described embodiments are only some of the embodiments of the present disclosure, not all of them. The present disclosure can also be implemented or applied through different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that the following embodiments and features in the embodiments may be combined with each other under the condition of no conflict. Based on the embodiments in the present disclos...

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Abstract

The invention discloses a design segmentation method for multiple FPGAs, and relates to the technical field of chip logic design. The method comprises the steps that S1, a logic circuit is modeled into a hypergraph: configuring grouping interconnection size resources and cutting grouping balance factors S2, supergraph coarsening: aggregating closely connected vertexes together to construct a sub-graph; S3, initial segmentation: traversing clusters without a connection relationship by using a greedy algorithm rule according to the sizes of partitions and a cutting grouping balance factor of theclustered sub-graphs, and allocating the clusters to different partitions; and S4, optimization adjustment: calculating the movable vertex income according to an FM algorithm, performing adjustment,and optimizing the cutting size. An optimal segmentation result can be obtained under the condition that interconnection constraint rules among the FPGAs are met in the segmentation process of the multi-FPGA prototype system.

Description

technical field [0001] The present disclosure relates to the technical field of chip logic design, and in particular to a design division method for multiple FPGAs. Background technique [0002] At present, with the rapid development of the IC chip industry, the logic design required for FPGA prototype verification is getting larger and larger. It is difficult for a large-scale FPGA in the industry to accommodate the logic functions of all chips. Users need to try to cut a large design into several small designs and configure them into multiple FPGAs, while ensuring that the logic functions of the entire design are correct and the performance is up to standard during runtime. Usually, the whole design segmentation process needs to take into account many factors and processing work, which is very energy-intensive and time-consuming. [0003] In the prior art, in order to solve the above-mentioned problems, traditional industry segmentation tools based on the graph theory min...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/347G06F30/392G06F115/12G06F111/04
CPCG06F30/347G06F30/392G06F2115/12G06F2111/04Y02D10/00
Inventor 李伟张吉峰
Owner S2C
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