SOC chip bus dynamic multi-level frequency adjustment circuit and method

Abstract

The invention provides a SOC chip bus dynamic multi-level frequency adjustment circuit and method. The circuit comprises a clock generation unit, a clock management unit, a bus frequency mapping tablestorage unit, master device monitoring control units, bus request blocking units and a bus transmission state monitoring unit. The bus frequency mapping table storage unit stores a multi-level bus frequency mapping table which presets the bus frequency corresponding to working scenes of the master devices. The clock management unit receives a working state of each master device sent from each master device monitoring control unit and an idle state of the entire bus sent from the bus transmission state monitoring unit, and controls relevant units such as the clock generation unit to complete abus dynamic frequency conversion process according to the working state of the master device, or controls the clock generation unit to turn off the clock of the entire bus according to the idle stateof the entire bus. Thus, the frequency of the bus can be adjusted dynamically in time to adapt to the current bus load, and the best energy efficiency ratio can be obtained.

Description

technical field [0001] The invention relates to an SOC chip, in particular to an SOC chip bus frequency adjustment circuit and method. Background technique [0002] With the rapid increase in the scale of SOC chips, the power consumption of large-scale SOC chips is also rising rapidly in the same proportion, but the battery capacity of mobile devices is limited, so how to control the power consumption of large-scale SOC chips has become an important issue in the consumer electronics industry. research topics. In the current technology, except that the frequency of the CPU is often changed to adapt to different computing loads, the clock of the transmission bus usually uses a fixed frequency, or the entire bus clock can only be shut down by software when the entire bus is not used for a long time. Because the bus is responsible for the interconnection of the entire SOC chip, it is an important component circuit in the SOC. There are usually many buses in the SOC, but usually...

AI Technical Summary

Problems solved by technology

Due to the complexity of the bus behavior and the slow response of the software behavior (the software instruction operation is usually hundreds of cycles or even longer corresponding to the hardware clock), the software cannot accurately detect or issue blocking behaviors in time, so it is difficult for the software to perform on time. And precise clock control, so that the bus clock can only be opened to the maximum or the whole is turned off

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