Digital receiver module, signal processing method thereof, and radio frequency card wiring method

Abstract

The invention discloses a digital receiver module, a signal processing method thereof, and a radio frequency card wiring method. The digital receiver module comprises a signal collection unit, a clock management unit, a synchronous speed reduction processing unit, and a signal processing unit. The clock management unit supplies a superspeed sampling clock for the signal collection unit, and provides a synchronous speed reduction processing clock for the synchronous speed reduction processing unit, wherein the synchronous speed reduction processing clock is coherent with the sampling clock. The signal collection unit achieves the sampling and single-bit quantification of a radio-frequency input signal, and outputs superspeed single-bit collection data. The synchronous speed reduction processing unit enables one-path superspeed serial data to be converted into 16-path high-speed parallel data through first level speed reduction processing. The signal processing unit provides an on-line adjustable time delay code value in the synchronous speed reduction processing unit, and completes the real-time processing of high-speed parallel data. The invention also discloses the signal processing module for the digital receiver module, and the radio frequency card wiring method for the digital receiver module.

Description

technical field [0001] The invention relates to a digital receiver module, in particular to an ultra-wideband single-bit digital receiver module, a signal processing method of the digital receiver module, and a radio frequency card wiring method of the digital receiver module. Background technique [0002] The ultra-wideband single-bit digital receiver can realize real-time digital processing of large instantaneous bandwidth signals by reducing the quantization accuracy of ADC and simplifying Fourier transform, and it is small in size and low in cost. Therefore, it is widely used in electronic warfare and broadband communication systems be widely used. The ultra-wideband single-bit digital receiver generally includes a signal acquisition unit, a clock management unit, a synchronous deceleration processing unit, and a signal processing unit, which together complete ultra-high-speed single-bit acquisition of input radio frequency signals and synchronous deceleration of ultra-h...

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Problems solved by technology

[0005] However, in the process of implementing the present invention, the inventor found that the problem of the prior art is that the two-stage synchronous deceleration process needs to divide the input clock signal twice and distribute the clock three times, which increases the complexity of the clock management unit. The reliability of the entire receiver is reduced; the phase relationship between the clock and data signals of each level of speed reduction processing is difficult to achieve precise control, and bit errors will occur during the speed reduction processing, which will affect the stable operation of the entire receiver

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