605 results about "Phase selection" patented technology

Embodiments describe new mechanisms for signalized intersection control. Embodiments expand inputs beyond traditional traffic control methods to include awareness of agency policies for signalized control, industry standardized calculations for traffic control parameters, geometric awareness of the roadway and/or intersection, and/or input of vehicle trajectory data relative to this intersection geometry. In certain embodiments, these new inputs facilitate a real-time, future-state trajectory modeling of the phase timing and sequencing options for signalized intersection control. Phase selection and timing can be improved or otherwise optimized based upon modeling the signal's future state impact on arriving vehicle trajectories. This improvement or optimization can be performed to reduce or minimize the cost basis of a user definable objective function.

A multiple-input-multiple-output (MIMO) receiving system configured for receiving multiple transmission layers is provided herein. The system includes a plurality of beamformed tunable receiving antennas configured to receive a plurality of transmitted layers; and a control module configured to select for the beamformed antennas a single set of discrete weights for tuning said antennas for all of the transmitted layers so that the weights are selected for optimal performance of said receiving system, wherein said selection is carried out based on an extended Maximal Ratio Combining (MRC) metric or other quality metric measured by the MIMO baseband module, and using said measured metric separately for each beamformed antenna to determine gain or attenuation independently of phase selection.

Provided are a high-voltage circuit breaker opening and closing time online monitoring apparatus, a smart multi-dimensional big data analyzing expert system for a high-voltage circuit breaker in a power grid, and methods therefor. The opening and closing time online monitoring apparatus includes a circuit breaker opening and closing events database, a circuit breaker opening and closing time online monitoring module, and a human machine interaction interface. Data in the circuit breaker opening and closing events database is derived from a SCADA and a measurement and control apparatus thereof, a circuit breaker phase selection opening and closing apparatus, a relay protection apparatus and a relay protection information system, and a fault recording apparatus and a fault recording system of each of a substation and a converter station. The circuit breaker opening and closing time online monitoring module includes various modules, and cloud databases for such online monitoring are created.

A signal generator, such as a fractional-N PLL, has, in its feedback signal path, a divider, a phase circuit, and a fractional accumulator that generates control signals for the divider and the phase circuit. The divider control signal controls the divisor value applied by the divider. In one embodiment, a phase selector selects, based on the phase-circuit control signal, one of a plurality of phase-shifted output signals generated by the PLL's main signal path (e.g., by a multi-phase VCO) and the divider generates the feedback signal for the PLL from the selected signal. In another embodiment, the divider generates a divided signal from one of the phase-shifted output signals, and a phase mixer generates, from the divided signal, a plurality of phase-shifted divided signals and selects, based on the phase-circuit signal, one of the phase-shifted divided signals as the PLL's feedback signal.

A complete digital receiver symbol timing synchronizing apparatus of the digital communication technique domain, includes an interpolator, a sampling clock frequency error estimation module, a loop filter, an interpolation controller, a sampling clock phase error calculation module and a sampling phase selection controller, wherein, the sample value of the system over-sampling is taken as the input of the interpolator; the sample value result after the regulation of the interpolator output is taken as the input of the sampling clock frequency error estimation module, for finding the correct sampling point position; the sampling phase selection controller sends out commands to control a lower sampling device, thereby making the lower sampling device complete sampling in the optimum time; the output result of the lower sampling device is taken as the input of the sampling clock frequency error estimation module, for calculating the sampling clock frequency bias; the interpolation controller controls the work process of the interpolator according to the sampling clock frequency bias fed in from the loop filter, for implementing the exactness correction to the sampling values. The loop circuit structure of the invention is quite simple, and is realized by hardware in the digital domain.

An antenna system including a coverage antenna (2) with a coverage beam pattern; and an auxiliary antenna (3) with an auxiliary beam pattern. The auxiliary beam pattern is arranged to perform sidelobe suppression, null steering, null addition, or null-fill. In the case where the auxiliary antenna is used to perform sidelobe suppression, the auxiliary beam pattern has a mainlobe with: an amplitude lower than an amplitude of a mainlobe of said coverage beam pattern; a width lower than a width of said mainlobe of said coverage beam pattern; a phase different to a phase of a sidelobe of said coverage beam pattern; and a direction which is selected so as to at least partially suppress said sidelobe.

The invention relates to a low-voltage intelligent circuit breaker with a plastic shell. The low-voltage intelligent circuit breaker comprises a switch base and a switch cover, wherein the switch base is provided with four longitudinal through grooves and a transverse through groove penetrating through the longitudinal through grooves, a vacuum electromagnetic switch, a current transformer and a storage capacitor are sequentially installed in three longitudinal through grooves; another vacuum electromagnetic switch and another storage capacitor are sequentially installed in the other longitudinal through grooves, and a zero sequence transformer is installed in the transverse through groove; and a control circuit board is fixed at the upper middle of the switch base, a power module, a charging module, a phasing voltage transformer, three voltage transformer for phase selection, two main processors and two auxiliary processors, wherein the display circuit board is located in the upper middle of the control circuit board and embedded in the switch cover and provided with a display screen, a red indication lamp, a green indication lamp, a switching-in operation button, a switching-off operation button and the like. The invention has the advantages of small volume, compact structure, convenience for use and installation and capability of truly realizing comprehensive intelligence of digital protection, automatic control and communication function.

A single-phase-to-earth fault processing device for a neutral non-effectively grounded distribution network includes a split-phase arc quenching device connected between earth and a three-phase bus of the distribution network, and a controller with an input end connected with a single-phase-to-earth phase selection device of the distribution network. The split-phase arc quenching device includes a multiphase switching device which operates independently for each phase, and a fuse connected in series with the multiphase switching device. The controller is for controlling opening and closing of three single-phase switches, in the multiphase switching device. A single-phase-to-earth fault processing method firstly controls the split-phase arc quenching device to preprocess the fault. If the fault still exists, through a ground resistor a zero-sequence current is generated on a fault line. After delaying to wait for a line to isolate a fault section, a ground connection of the neutral is cut, to restore the distribution network.

The invention discloses a method for initially positioning and starting a switched reluctance motor without a position sensor, and belongs to the technical field of control of the switched reluctance motor. The method comprises the following steps of: setting an inductance bottom threshold value LLow and an inductance top threshold value LHigh based on the basic characteristic that the inductance of the switched reluctance motor periodically changes with the position of a rotor; injecting short pulses into each phase winding and calculating inductance values according to a phase voltage equation; judging phases which can be currently switched on according to the relation among each phase inductance calculated value and LLow and LHigh and selecting estimated phases of an initial position angle at the same time; and establishing a phase inductance mathematical model to obtain angle information in the selected phases by using the relation between the inductance mathematical model and the inductance calculated values. Though the method, an initial switch-on phase selection signal can be accurately acquired and the initial position angle of the rotor can be calculated at the same time, so the switched reluctance motor can be started and initially positioned without the position sensor, an algorithm is simple and generality is high.

An open-loop data recovery apparatus and method utilizing an oversampling technique is provided, by which the occurrence of data transitions is counted and a proper sampling clock phase is decided. Counters with variable thresholds are used to monitor the occurrence of phase transitions for a phase selection circuit to determine a preferred phase for recovery of sampled data. The thresholds of the counters are further adjusted in reference with the preferred phase decided by the phase selection circuit.

The invention relates to a fault phase selection method based on a current break variable, which belongs to the technical field of fault judgment of a power system and constructs a fault phase selection coefficient by use of the current break variable to realize selection of the fault type and fault phase. The method comprises the following steps of: constructing a fault phase selection coefficient by use of the proportional relationship between the fault current of one phase and the difference between the fault current of other two phases measured by a protection device of a high-voltage line; and then analyzing the different characteristics of the coefficient in various fault conditions to realize fault phase selection of the power system. The method can accurately identify the fault phase within a cyclic wave after the fault occurs, has relatively high sensitivity to various types of faults, is not influenced by the fault position, transition resistance and load current, and has relatively high reliability and good selectivity; and meanwhile, the method has enough sensitivity to the fault phase selection on the weak power side.

This invention presents a novel receiver architecture for full-duplex multi-level PAM systems. The receiver employs an Analog-to-Digital Converter (ADC) that has a sample rate flexibly specified as (N_s+1)/N_s baud rate where N_s is an integer equal or greater than 1. A fractional-spaced echo canceller is used to cancel the echo at the ADC output. The use of a fractional sampling rate higher than the baud rate also enables the timing recovery function be implemented in the digital domain and hence eliminates the need of using the complex analog phase selection circuit. The receiver is also capable of fast, blind start-up by use of a decision feedback equalizer with unity main tap and a soft level slicer. The timing phase can be optimally located using a derivative channel estimator. Once the “eye-open” condition is achieved, the channel equalization is switched to the use of linear equalizer coupled with an error feedback equalizer to alleviate the error propagation problem associated with the decision feedback equalizer.

In one embodiment of the invention, a phase selection unit for generating a recovered clock signal (SCLK), a phase select signal generator generates a phase select signals in response to a FWD signal and a BWD signal from a digital filter. The digital filter asserts the FWD signal if the phase of a SDIN (serial digital input) signal leads the phase of the recovered clock signal, and asserts the BWD signal if the phase of the SDIN (serial digital input) signal lags the phase of the recovered clock signal. A multiplexer receives a number of given clock signals arranged in a predetermined phase order and outputs selected first and second output clock signals, each being one of the given clock signals. A phase interpolator receives the selected first and second output clock signals from the multiplexer to generate the recovered clock signal having a phase that is phase interpolated between the phases of the first and second output clock signals.

The invention discloses a self-learning switching-on phase control method adopted by a phase selection switching-on device, which is applied to the phase selection switching-on control of electric equipment in an alternating current station and a direct current converter station. The self-learning switching-on phase control method is characterized in that the self learning of an optimum object throw phase based on the circuit breaker mechanical action deviation and real-time digital data service (RDDS) function combination and the action record comparison correction is adopted. The strong switch characteristic self learning capability is realized, the switch characteristics can be accumulated according to the in-site operation, and the real-time correction is carried out. The intelligent correction is realized in the application, and the limitation of determining the optimum object phase by the artificial factors or the empirical values is avoided.

The invention discloses an intelligent phase selection switch controller, and belongs to the technical field of power electronics. The intelligent phase selection switch controller comprises a microprocessor, a power supply circuit, a displaying circuit, a failure alarming circuit, a voltage zero point capturing signal collecting processing circuit, a current zero point capturing signal collection processing circuit, a voltage failure detection signal collection processing circuit, a current failure detection signal collection processing circuit, a magnetic latching relay driving circuit and a switch controller mode conversion circuit. The microprocessor receives input commands and signals input by the four signal collection circuits, carries out processing on the input signals, and controls the magnetic latching relay to achieve zero passage switching. The intelligent phase selection switch controller can achieve flashy-flow-free input of a capacitor and electric-arc-free disjunction of relay contactors, can detect and automatically compensate action time error of zero switching, and can carry out detection on the performance of the relay, so that a user an replace different magnetic latching relays according to actual needs.

A tester for testing high-speed serial transceiver circuitry. The tester includes a jitter generator that uses a rapidly varying phase-selecting signal to select between two or more differently phased clock signals to generate a phase-modulated signal. The phase-selecting signal is designed to contain low-and high-frequency components. The phase-modulated signal is input into a phase filter to filter unwanted high-frequency components. The filtered output of the phase filter is input into a data-transmit serializer to serialize a low-speed parallel word into a high-speed jittered test pattern for input into the transceiver circuitry.

The invention relates to an alternating current high-voltage vacuum circuit breaker, which is characterized in that the invention comprises a case body, a vacuum arc extinguish chamber is seated and connected to the case body, an electromagnetic repulsive force mechanism is disposed in the case body, the mechanism comprises an open coil and a close coil which form a fixed gap, a repulsion disk arranged in the gap, a repulsion rod which is fixedly penetrated by the equipped repulsion disk, a retention capacity rod of a composite disc spring retention force structure connected with the lower end of the repulsion rod, a catch spring fixed on the retention force rod and at least two pieces of disc springs top-arranged on the catch spring. The upper end of the electromagnetic repulsive force is connected with a closing buffer gear which comprises a spring frame structure and a hydraulic cylinder, further, the closing buffer gear comprises an intelligent pulse generator. Because the invention employs the electromagnetic repulsive force mechanism, employs bi-stable composite disc springs to retain, employs the closing hydraulic pressure buffer gear to inhibit closing bouncing, and employs a photoelectric sensor to realize position returning, thereby belonging to the advanced design at home and abroad, therefore, the invention can be widely applied to the field of fault current limiters, phase selection switches, solid change-over switches and the like.