Symbol timing synchronizing apparatus for complete digital receiver

Abstract

A complete digital receiver symbol timing synchronizing apparatus of the digital communication technique domain, includes an interpolator, a sampling clock frequency error estimation module, a loop filter, an interpolation controller, a sampling clock phase error calculation module and a sampling phase selection controller, wherein, the sample value of the system over-sampling is taken as the input of the interpolator; the sample value result after the regulation of the interpolator output is taken as the input of the sampling clock frequency error estimation module, for finding the correct sampling point position; the sampling phase selection controller sends out commands to control a lower sampling device, thereby making the lower sampling device complete sampling in the optimum time; the output result of the lower sampling device is taken as the input of the sampling clock frequency error estimation module, for calculating the sampling clock frequency bias; the interpolation controller controls the work process of the interpolator according to the sampling clock frequency bias fed in from the loop filter, for implementing the exactness correction to the sampling values. The loop circuit structure of the invention is quite simple, and is realized by hardware in the digital domain.

Description

technical field [0001] The invention relates to a synchronization device in the technical field of digital communication, in particular to a symbol timing synchronization device for an all-digital receiver. Background technique [0002] With the development of digital signal processing technology and the reduction of device cost, the transceiver of digital communication system is developing towards the direction of full digitalization and softwareization (software radio architecture). Symbol timing is the key technology of all-digital receiver, and it is the basis of correct sampling judgment. The quality of system timing will directly affect its performance. This is also the most challenging part of an all-digital receiver. Due to the channel transmission delay and the clock offset caused by the unstable operation of the oscillator, the sampling clock frequencies at the two ends of the transceiver will not be exactly the same, so there is a small deviation between the samp...

AI Technical Summary

Problems solved by technology

However, since the symbol synchronization device completes the two processes of sample interpolation and downsampling at the same time, it is impossible to select the sample point of oversampling, so that it cannot ensure that the final output result is the best obtained under the condition of maximum signal-to-noise ratio. The optimal value, especially in the case of severe channel noise interference or high modulation order used by the system, will lead to a decline in the performance of the receiver

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