Reconfigurable floating-point operation device based on CORDIC algorithm

A floating-point calculation and algorithm technology, which is applied in calculation, instrumentation, electrical digital data processing, etc., can solve problems such as limited convergence range, long algorithm delay, and unsatisfactory calculation accuracy, etc., and achieve simplified iterative calculation formulas, low delay, The effect of shortening the clock cycle

Active Publication Date: 2018-12-21
BEIJING INSTITUTE OF TECHNOLOGYGY
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Problems solved by technology

However, the traditional CORDIC algorithm has problems such as limited convergence range and long algorithm delay. Repeating certain iterations can expand the convergence domain, but it will cause the scaling factor to be non-constant, requiring additional hardware logic to operate. Scaling-Free CORDIC The algorithm adopts the method of Taylor series approximation, which can avoid the calculation of the scaling factor and reduce the number of iterations. However, most of this method is applied to the fixed

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  • Reconfigurable floating-point operation device based on CORDIC algorithm
  • Reconfigurable floating-point operation device based on CORDIC algorithm
  • Reconfigurable floating-point operation device based on CORDIC algorithm

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Embodiment Construction

[0028] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0029] The calculation of trigonometric functions is realized in the circular coordinate system, and the calculation of the sine and cosine functions is completed in the rotation mode, and the initial value is X 0 =K 1 , Y 0 = 0, Z 0 = θ, the output is X n =cosθ,Y n =sinθ, the convergence area is -99.827°≤θ≤99.827°; the calculation of the arctangent function is completed in the vector mode, and the initial value is set to Z 0 =0, the output is Z n =tan -1 (Y 0 / X 0 ), the convergence region is -99.827°≤tan -1 (Y / X)≤99.827°.

[0030] The multiplication and division operations are implemented in the linear coordinate system, and the multiplication operation is completed in the rotation mode, and the initial value is Y 0 =0, the output is Y n =X 0 / Z 0 , the region of convergence is |z 0 |0 =0, the output is Z n =Y 0 / X ...

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Abstract

A reconfigurable floating-point arithmetic device based on CORDIC algorithm comprises a preprocessing module for completing input data from IEEE-754 standard, and maps it into the convergence region;a series-parallel hybrid reconfigurable CORDIC iterative unit module. The iterative operation part of CORDIC algorithm is composed of two parts: rotation modules A and B, wherein, the rotation moduleA is used to realize serial pipeline structure to maximize module reuse, the rotation module B is based on parallel prediction method of rotation direction and adopts tree adder structure to realize parallel structure in rotation mode; in the post-processing module, the corresponding result output is selected according to the encoded signal of the pre-processing module, and the mantissa normalization processing is completed to output the single-precision floating-point data format calculation result. The invention has the characteristics of simple principle, low delay, high precision and low hardware cost.

Description

technical field [0001] The invention belongs to the technical field of a floating-point arithmetic unit in radar real-time imaging processing, and in particular relates to a reconfigurable floating-point arithmetic device based on a CORDIC algorithm. Background technique [0002] In the real-time imaging processing of on-board synthetic aperture radar (SAR), in order to achieve higher resolution, a large amount of data needs to be stored and downloaded, and the imaging processing algorithm has a huge amount of computation, which not only poses a challenge to real-time processing , but also brought great difficulties to the hardware implementation. In particular, the calculation of the phase compensation factor in the Chirp Scaling (CS) algorithm includes multiple nonlinear operations such as single-precision floating-point trigonometric functions and square root. These operations are generally implemented on hardware by methods such as lookup table, polynomial fitting, and ...

Claims

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Application Information

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IPC IPC(8): G06F7/57
CPCG06F7/57
Inventor 胡善清方琳琳李炳沂谢宜壮陈亮
Owner BEIJING INSTITUTE OF TECHNOLOGYGY
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