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VLSI system structure of bit plane encoder

An encoder and bit plane technology, applied in image coding, instruments, television, etc., to reduce access and reduce clock cycles

Inactive Publication Date: 2012-03-28
SHANDONG UNIV
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Problems solved by technology

[0004] The purpose of the present invention is to solve the deficiencies in the existing bit-plane coding hardware acceleration scheme, and provide a coefficient-hopping bit-plane coding based on column processing with the advantages of simple structure, fast operation speed, and effective improvement of system operating efficiency. VLSI system architecture of the

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Embodiment

[0039] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0040] combine first figure 1 The algorithm of this embodiment is briefly described. The idea of ​​bit-plane coding is to encode the most important information first, that is, to encode the amplitude information with a larger weight first, so that with the subsequent code stream organization, the final code stream can obtain the characteristics of progressive transmission. After wavelet transformation and quantization, the slice component matrix becomes a subband matrix of integer coefficients. Each subband is divided into rectangular code blocks of the same size (except for the code blocks on the border). Each code block can be decomposed into bit planes, that is, bit layers one by one. The encoding is encoded plane by plane from the most significant bit-plane to the lowest bit-plane of the code block. The bit-plane encoder performs an independent ...

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Abstract

The invention discloses a VLSI system framework of a bit plane coder and comprises a master controller, a channel attribution judging device, a register controller, a register set, each channel coding module, and modules such as a coding primitive module and the like. The system framework realizes coding primitive operation by adopting a mode of a combined circuit to improve generation speed of acontext judgment pair, directly controls and realizes run coding logic in a clearing channel module to simplify a circuit structure, and adopts a coefficient jump method based on column treatment when scanning each channel to reduce clock period wasted in a scanning process greatly, so as to enhance coding speed.

Description

technical field [0001] The invention belongs to the technical field of VLSI design, and relates to a VLSI system architecture of a bit plane encoder. Background technique [0002] JPEG2000 is a new generation still image compression standard proposed by the Joint Photographic Experts Group. Due to the adoption of many innovative technologies, the standard has a series of excellent features: high compression rate; PSNR progressive; code stream random access; region of interest coding; both support lossy compression and lossless compression, etc. Compared with the existing JPEG standard, JPEG2000 adopts Discrete Wavelet Transform (DWT) as its core transform algorithm, and Embeded Block Coding with Optimized Truncation (EBCOT) as the core code Algorithms are far superior to traditional algorithms such as JPEG in terms of coding efficiency and restored image quality, and will surely occupy a dominant position in the field of still image compression. [0003] However, the adopt...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06T9/00H04N7/26H04N19/42
Inventor 王洪君孙红艳刘速栗华李庆华
Owner SHANDONG UNIV
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