Random access memory initialization

A random access memory, random access storage technology, applied in static memory, digital memory information, information storage and other directions, can solve problems such as performance degradation

Inactive Publication Date: 2009-01-14
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This can cause considerable performance degradation

Method used

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  • Random access memory initialization
  • Random access memory initialization
  • Random access memory initialization

Examples

Experimental program
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Embodiment Construction

[0017] Figure 3 shows a memory structure embodying the invention, which should incorporate Figure 4 flow chart to read.

[0018] When a reset event occurs (step 50 ), a logic signal is clocked into the reset input of flag generator 36 and clocked into the S terminal of RS flip-flop 32 . Thus, the Q output of flip-flop 32 is set to logic "1" to indicate the initialization phase (step 52). A logic "1" is present at terminal S of the logic multiplexer 40, which results in a logic "0" output at the multiplexer output O (step 54). This is also fed back to the token generator 36 to indicate that all tokens are free to use and can be issued in sequence (step 56). As such, the tag state is assumed to be logic "0" to indicate that no tags are in use, even though some tags may be present in the memory address location.

[0019] In this example, tag generator 36 is free to issue tags via write address port 18 and update address space 12, starting at address 000 and proceeding to addre...

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PUM

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Abstract

The invention discloses a random access memory initialization method and circuit. The circuit includes a memory having a set of address spaces to which tag data is written and read from, each address space having tag status bits, and a tag generator to allocate tag data to the memory address spaces. When a reset occurs, this logic circuit provides a logic "0" to the flag generator to disable the status bit check control so that all flags can be issued sequentially. New tag data is sequentially allocated to this address space, and the respective status bits are updated or maintained at logic "1". When all address space has been allocated, this logic provides the actual state of this status bit to the flag generator to control subsequent allocations. The method and circuit of the present invention avoid all resets of status bits in the memory and thereby save the clock cycles required to initialize these status bits.

Description

technical field [0001] The present invention relates to initialization of random access memory (RAM). Background technique [0002] In a packet-based communication system, the initiator sends a read request packet to the target device. The target device returns a response packet after a period of time. For efficient sending of packets, the device should be able to send many read request packets before receiving a response packet from the target device. To support this, the initiator assigns a tag / marker to each read request packet. In this way, the initiator is able to identify and process response packets. The target device shall use this same tag / flag in the response packet. Once this two-way transaction is complete, the token is released and can be reused. For each outstanding mark, the initiator needs to remember the attributes of the read request packet, such as address, data length, etc., until the response packet is received. [0003] At the start of a session, ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C7/20G11C11/413H04L12/28
CPCG11C7/20
Inventor S·N·安比卡尔G·G·库鲁普A·米斯拉
Owner INT BUSINESS MASCH CORP
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