118 results about "Digital computation" patented technology

A technique is provided for determining ownership interest allocation for a business, wherein transactions of contributors with the business are grouped into contributor transaction classes (CTCs), and a contribution value is calculated for the contributor transactions in each CTC to indicate the contribution of each transaction to the value of the business, using one or more performance metrics for each CTC, and lastly, at least one ownership interest award rule for a contributor is determined, based on the calculated contribution values for the CTCs. The technique can be performed with a digital computer and can provide real-time dynamic measures of ownership interest allocation.

The present invention performs a digital computation with a lower than worst-case-required clock period (i.e., a faster clock), and at the same time performs the same computation with a larger, worst-case-assumed, clock period (i.e., a slower clock) on a second system with identical hardware. The outputs from the computations are compared to determine if an error has occurred. If there is a difference in the two answers, the faster computation must be in error (i.e., a miscalculation has occurred), and the system uses the answer from the slower system. In one embodiment, the present invention utilizes two copies of the slower system that each run half as fast as the main system. However, the two copies produce results in the aggregate at the same rate as the main system, which is running at a much faster rate than possible without the invention. Hence the present invention improves performance (e.g., speed), albeit with more hardware. Advantageously, the present invention dynamically adapts to achieve the best performance possible under the actual operating conditions.

The invention belongs to Video decoder IC design field. The character is in that: to the same operation among the prediction formulas in 17 different prediction modes of 4x4 block with 16 pixels adopting digit computation strength cut method to remove computation redundance; providing a in-frame predictor system with high degree of parallelism, which can process the predicted values of 16 pixels within every clock cycle. From the results achieved, compared to the design with the use of reconstruction, this invention can decrease circuit area under same parallelism and simplifies the control logic.

The invention provides a fast reflector electric control system for improving the pointing accuracy of a laser emission system, and relates to the field of fast reflector control. The fast reflector electric control system solves the problem that an existing control system cannot effectively improve the pointing accuracy of a laser emission system. The fast reflector electric control system comprises a main control computer, a servo controller connected with image processing software and an azimuth and elevation encoder in an infrared camera and a driver. The servo controller receives control instructions of the main control computer to execute corresponding actions, feeds tracking errors, positions and state data back to the main control computer, meanwhile receives data of the azimuth and elevation encoder to perform digital computation to output PWM signals, and receives image target-missing quantity data of the image processing software to control a fast reflector to perform real-time tracking. The driver is connected with the servo controller and an azimuth and elevation voice coil motor, amplifies the PWM signals to convert the PWM signals to be in a double-H-bridge PWM mode, and outputs motor control signals to control running of the motor. The fast reflector electric control system is high in control accuracy and easy to operate.

HEN2, which is a combination of signals in which at least one of two adjacent digits at any digit position of one or more digits of a 2-based three digit redundant binary number with one signal of three digits {n, o, p} each expressing value {-1, 0, 1} as a one-digit signal is a signal "o" expressing zero, is handled as one set of notation, not as a subset of the three digit redundant binary number.

The invention relates to a real time monitoring data-based mine tailing dam instability risk evaluating method and belongs to the technical field of special-purpose digital computation or data processing methods. The method helps overcome defects of technologies of prior art that cannot be applied to determining magnitude of dam slope instability risk, risk sources and the like. According to the real time monitoring data-based mine tailing dam instability risk evaluating method, based on a condition that monitoring data is obtained and a representative instability mode is determined; failure probability and slide area of all instability modes are used for determining instability risk thereof, mine tailing dam instability risk can therefore be quantified, mine tailing dam instability risk can be evaluated mostly based on the monitoring data, mode grouping is realized and the representative instability mode is selected according to correlation of anti-sliding stability safety factors of shallow-layer and deep-layer instability modes, and frequency and a glide plane of the representative instability mode which is regarded as an instability mode with maximum danger are used for evaluating risk in a quantified manner. The real time monitoring data-based mine tailing dam instability risk evaluating method is characterized by scientific property, visual property, reasonability and feasibility; scientific basis is provided for mine tailing dam operation safety management and risk control.

The invention provides a transformer winding temperature measuring device based on a fluorescent fiber technique, which comprises a fiber temperature sensor, a photoelectric converter, a light source driving module, an amplifier module, a light source trigger module, a synchronous collecting AD converter, a master control CPU module and an IEC61850 communication protocol conversion module. The transformer winding temperature measuring device based on the fluorescent fiber technique has the advantages that: an ARM processor is used for generating a reference drive pulse, and meanwhile, a drive pulse and a reverse pulse of the ARM processor are used as reference signals, and high-speed synchronous sampling is utilized to collect the reference signals and fluorescent signal, and the delay between collecting channels is eliminated; the demodulation for the fluorescent signal is finished in the ARM processor, so that the analog circuits, such as an analog phase-locked loop, a filter, and the like, are omitted, the system complexity is greatly reduced and the reliability is greatly improved; and the digital computation is adopted, so that consistency of a collecting device is good.

The invention discloses a temperature-compensation-free current measurement method which uses modulation demodulation time division multiplexing technology, conducts modulation demodulation on sensing subcircuits of optical fiber sensing rings with two different temperature characteristics simultaneously, obtains measured values of the two sensing rings, and conducts digital computation according to temperature models of the two sensing rings to obtain the final measured value. The invention further discloses a device for achieving the method. The device comprises a light source, an optical fiber coupler, a two-channel phase modulator, a double refraction optical fiber delay line, the two sensing rings with different temperature characteristics, a detector and an electric signal demodulation unit, and two modulation channels of the two-channel phase modulator form two sensing subcircuits with the double refraction optical fiber delay line and one sensing ring. A temperature-compensation-free fiber optical current transformer and the method use test current demodulation values corresponding to two fiber rings with different temperature performances to calculate measurement current values without temperature influences, and accuracy, reliability and stability in a whole temperature scope are guaranteed.

An embodiment of a method and a related apparatus for digital computation of a floating point complex multiply-add is provided. The method includes receiving an input addend, a first product, and a second product. The input addend, the first product and the second product each respectively has a mantissa and an exponent. The method includes shifting the mantissas of the two with smaller exponents of the input addend, the first product, and the second product to align together with the mantissa of the one with largest exponent of the input addend, the first product and the second product, and adding the aligned input addend, the aligned first product and the aligned second product.

The embodiment of the invention discloses an accumulation circuit for floating-point numbers and a realization method thereof, relating to the technical field of digital computation. The method comprises the following steps of: performing a negation operation, an exponent arithmetic operation, a symbol sum arithmetic operation, an exponent matching operation, a double-circuit accumulation operation, an addition operation, a symbol selection operation, a normalization operation, an overflow handling operation on at least two floating-point number signals, and outputting the accumulation result of the combination of the input signals. The accumulation circuit for floating-point numbers and the realization method for the same disclosed by the invention are suitable for floating-point number arithmetic.

A controller for an adjustable-frequency oscillator includes a first counter supplied with a stop-count value to count adjustable-frequency oscillator cycles divided by the ratio of desired frequency to reference oscillator frequency, to produce a stop signal when the first counter reaches the stop-count value. A second counter counts cycles of a reference oscillator starting from an initial number related to the stop-count value. The second counter stops counting and produces an end-count when the second counter receives the stop signal from the first counter. A resonant tank circuit includes a bank of capacitors with switches to select resonant tank circuit capacitors. The switches are selectively controlled using the end-count in the second counter. The stop-count value is set for the first counter so that the end count number in the second counter using a ones-complement binary format can be used to iteratively set the switches with minimal digital computation.

A portable radio system, a portable radio equipment to be used in the same and a frequency error prediction method can be adapted to large frequency error by making tap number smaller and frequency error smaller. The portable radio system employs an automatic frequency control for detecting a frequency shift of an internal oscillator of a portable radio equipment with reference to a received wave transmitted from a base station having higher precision of frequency and adjusting the frequency of the internal oscillator by feeding back the frequency shift to the internal oscillator. Coordinate rotation digital computation (CORDIC) is employed for calculation of arctangent in the automatic frequency control.

A graphics endowed, computer-based system, and an associated methodology, for performing diagnoses of medical problem-types. The system and methodology utilize (a) a digital computational engine, (b) a database operatively connected to the engine including a storage medium which contains medical-problem-type-related, anatomical, graphics data components, some of which have characteristics of non-normalization that are linked through relevance short-cutting to other components which have characteristics of normalization, and (c) a user-interactive, graphical interface including a display screen operatively connected both to the engine and to the database, operable under engine control to display selected ones of the mentioned graphics data components in both user-interactive sensitized-input, and user-informative-output, modes during medical problem-type diagnosis performed by the system.

Apparatus and method for generating signal gain coefficients for use in packet data communication between a single-input-single-output (SISO) transceiver and a single-input-multiple-output/multiple-input-single-output (SIMO/MISO) transceiver. Coordinate rotation digital computation (CORDIC) techniques are used to generate transmit channel coefficients which are substantially complementary to receive channel coefficients representing relative strengths of individual signals received via multiple spatially diverse antenna elements and corresponding to a wireless data signal originating from a particular SISO radio frequency (RF) transceiver. Using such transmit channel coefficients to produce outgoing RF signals for transmission via the same antenna elements and reception by such particular SISO RF transceiver provides for signal transmission and reception diversity.

Hardware and processes are provided for efficient interpretation of multi-value signals. The multi-value signals have a first voltage range with is used to indicate multiple numerical or logical values, and a second voltage range that is used to provide control functions. In one example, the multi-value circuitry is arranged as a set of rows and columns, which may be cascaded together. The control function can be implemented to cause portions of rows, columns, or cascaded connections to be powered off, thereby saving power and enabling more efficient operation.

A computational method for implementation in an electronic digital processing system performs integer division upon very large (multi-word) operands. An approximated reciprocal of the divisor is obtained by extracting the two most significant words of the divisor, adding one to the extracted value and dividing from a power of two out to two significant words. Multiplying this reciprocal value by a remainder (initialized as the dividend) obtains a quotient value, which is then decremented by a random value. The randomized quotient is multiplied by the actual divisor, and decremented from the remainder. The quotient value is accumulated to obtain updated quotient values. This process is repeated over a fixed number of rounds related to the relative sizes in words of the dividend and divisor. Each round corrects approximation and randomization errors from a preceding round.

The invention discloses a method for measuring reliability of an electromechanical product and relates to a digital computation method which is specially applicable to specific application, in particular to a method for measuring the reliability of the electromechanical product based on a cloud theory. The reliability is measured and analyzed on a singlechip under the condition that stress data and strength data of the electromechanical product are provided. The method comprises the following step of establishing a reliable credibility curve, wherein the curve function is that: incomplete credibility of information is reflected on cloud thickness by means of thought of the cloud theory, the H(k) is clouded, reliable credibility cloud distribution Hi(k) is established, and an output result is intuitively displayed through a computer. By the method, the reliability of the electromechanical product is measured, random information can be processed, information and incompletely reliable information can be obscured, and the defect that the incompletely reliable information is not processed by a product reliability measuring scheme in the prior art is overcome.

The invention provides a method for achieving analog-to-digital conversion and associated apparatus. The analog-to-digital conversion apparatus comprises a digital module for receiving the digtal outputS of a plurality of pipelined analog-to-digital converters (ADC) that perform analog-to-digital conversion on a same analog signal. In addition, the digital module comprises a plurality of digital calculation pathes respectively corresponding to the pipelined ADCs, wherein each digital calculation path corresponding to an associated pipelined ADC of the pipelined ADCs is electrically connected with the associated pipelined ADC. The digital module performs digital calculations on the digital outputs to generate a calibrated digital output. The method and apparatus can realize high-speed analog-to-digital conversion without reducing the precision of analog-to-digital conversion not by high-precision low-speed ADC as the tool.