87 results about "Digital computation" patented technology

The invention relates to the technical field of digital computing and resource scheduling, in particular to a computing power resource intelligent scheduling and load balancing method. The method comprises the following steps: collecting performance indexes of a computing power node on different resource dimensions, and constructing a resource capability vector of the computing power node; extracting demand features of the calculation task on different resource dimensions, and constructing a task feature vector; matching the resource capability vector of the computing power node with the task feature vector to obtain an adaptation degree score; operation indexes of the computing power nodes are collected, comprehensive load scoring is carried out on the computing power nodes, and the current load states of the computing power nodes are obtained; and distributing calculation tasks based on the current load state of the computing power node and the adaptation degree score, and updating the current load state of the computing power node in real time. The problems that the resource utilization rate is low, the task response delay is high and the node load is unbalanced due to the fact that the computing power resources cannot be dynamically matched according to the task characteristics and the computing power node states in a traditional computing power resource scheduling method are solved.

The invention designs and provides a plurality of all-digital in-memory computing circuits based on ferroelectric transistors, and belongs to the field of integrated circuits. According to the invention, a plurality of all-digital in-memory computing circuits based on ferroelectric transistors are designed, weight data can be stored in the computing circuits to carry out all Boolean logic operations based on FEFET logic gate structures, and the all-digital in-memory computing circuit has important significance for breaking through a memory wall and a power consumption wall of a Von. Noiemann architecture. According to the FEFET in-memory calculation unit provided by the invention, relatively fixed weight data can be stored in a calculation circuit, so that the repeated transmission of the weight data is reduced, and the power consumption can be greatly reduced; meanwhile, due to full-digital calculation, multi-bit calculation precision cannot be sacrificed, the accuracy can be effectively improved, and the method is a potential technology applied to an artificial intelligence chip and an AI neural network.

Disclosed are various approaches for quantum computing enhanced language model (LLM) security protections. In some examples, an LLM communication such as an LLM prompt, or an LLM response can be received. A computing environment type decision between a digital computing environment or a quantum computing environment can be generated based at least in part on the LLM communication processing latency value and a threshold latency value. A selected one of the classical digital computing environment and the quantum computing environment can be used for an LLM security analysis based at least in part on the computing environment type decision.

The invention discloses a high-density RRAM sparse digital in-memory calculation method and circuit, and relates to the field of integrated circuit design, the high-density RRAM sparse digital in-memory calculation circuit comprises a plurality of RRAM in-memory calculation units, and the RRAM in-memory calculation units are configured to store data through a resistance value state and carry out digital calculation to obtain an output result; the digital logic units are electrically connected with the RRAM internal calculation units, and the digital logic units are configured to multiply and accumulate the output results to obtain multiply and accumulate results; the peripheral circuit unit is electrically connected with the calculation unit in the RRAM memory, and the peripheral circuit unit comprises a read path and a write path and is configured to read and write the resistance value state of the calculation unit in the RRAM memory at the same time; wherein the calculation units in one column of RRAM are correspondingly provided with one peripheral circuit unit. According to the invention, the data read-write efficiency can be obviously improved.

Quantitative phase imaging (QPI) is a label-free computational imaging technique that provides optical path length information of objects. Here, a diffractive QPI network architecture is disclosed that can synthesize the quantitative phase image of an object by converting the input phase information of a scene or object(s) into intensity variations at the output plane. A diffractive QPI network is a specialized all-optical device designed to perform a quantitative phase-to-intensity transformation through passive diffractive / reflective surfaces that are spatially engineered using deep learning and image data. Forming a compact, all-optical network that axially extends only ˜200-300λ (λ=illumination wavelength), this framework replaces traditional QPI systems and related digital computational burdens with a set of passive substrate layers. All-optical diffractive QPI networks can potentially enable power-efficient, high frame-rate and compact phase imaging systems that might be useful for various applications, including, e.g., on-chip microscopy and sensing.

The invention discloses a bearing fault diagnosis method and system based on a simulated physical neural network. The method comprises the following steps: S1, preprocessing a collected vibration signal to obtain a to-be-diagnosed signal; s2, executing a hybrid optimization algorithm to obtain an optimal transmission band parameter and an optimal weight parameter; s3, configuring a feature extraction module according to the optimal transmission band parameter, and writing the optimal weight parameter into a classification module; s4, inputting the to-be-diagnosed signal into a feature extraction module to obtain a simulation feature vector; s5, inputting the simulation feature vector into a classification module, and outputting a classification voltage signal; and S6, determining a fault type, and outputting a result. According to the method, a hybrid optimization algorithm is adopted, the ratio of the inter-class dispersion degree to the intra-class polymerization degree of the feature vectors is calculated, optimal adaptation of feature extraction and classification tasks is achieved, and the diagnosis precision and generalization ability are improved; by constructing a full analog domain signal processing architecture, analog-to-digital conversion and digital calculation are not needed, and microwatt-level power consumption and microsecond-level real-time response are realized.

The invention discloses a screen brightness uniformity detection method and system, relates to the technical field of digital computing, and solves the problems of low detection efficiency, inaccurate fault positioning and insufficient environmental adaptability test through automation, precision and multi-scene adaptability improvement. A touch response dimension score Scx and an environmental adaptability dimension score Sty are extracted through an online analysis module in combination with a deep learning technology, and a performance evaluation index Pczs is calculated; the performance evaluation screening module classifies the performance of the touch display screen through the evaluation content of the performance evaluation index Pczs, generates optimization or maintenance suggestions, and improves the detection efficiency and the fault positioning precision; the environment simulation module dynamically tests touch performance parameters and calculates an environment adaptability evaluation factor Htyx through high-temperature, high-humidity, strong-light and low-pressure environment scenes, so that the reliability and the stability of the touch display screen in an extreme environment are ensured, and the brightness uniformity of the screen is detected and evaluated more accurately.

The invention discloses a data processing method and system, electronic equipment and a readable storage medium, the method is applied to the data processing system, the data processing system comprises an analog calculation module, a digital calculation module and an analog-to-digital converter, the analog-to-digital converter is connected with the analog calculation module and the digital calculation module, and the analog calculation module is connected with the digital calculation module. The method comprises the steps that a first matrix is calculated according to input data based on an analog calculation module, analog data are obtained, and the first matrix comprises a matrix corresponding to the weight of a neural network; converting the analog data into digital data based on the analog-to-digital converter; based on the digital calculation module, a second matrix is calculated according to the digital data, target data are obtained, and the second matrix comprises a matrix used for describing the neural network topological structure. The analog calculation module and the digital calculation module are combined for calculation, so that the calculation power consumption is greatly reduced under the condition that the calculation precision is hardly influenced.

The present patent document provides a design of an efficient hybrid quantum classical computing system capable of information processing based on both quantum computing using different quantum states of qubits and classical digital computing using a digital processor including one or more graphics processing unit (GPU) processors.

1. Name of the Design Product: Calculator. 2. Use of the Design Product: This design product is used for digital calculation. 3. Design Key Points of the Design Product: Lies in the shape. 4. Picture or Photograph that Best Illustrates the Design Key Points: Perspective View 1.

Provided is a storage device that has a computation function and comprises: a plurality of differential logic tree cells; a plurality of digital differential sense amplifiers for respectively reading the computation results of the plurality of differential logic tree cells; a plurality of write circuits for writing data to each of the plurality of differential logic tree cells; and a digital computation circuit for performing computations by using the computation results from the plurality of digital differential sense amplifiers. Each differential logic tree cell includes: a memory cell which includes first and second magnetic storage elements for storing the data based on a change in a resistance value; and a differential logic circuit for performing logical computations by using the data stored in the memory cell and external data input from the outside.

A system for efficient element-wise and cross-vector maximum operations. One example system includes an input bus, an output bus, and a memory configured to store N / K elements of an N-element vector in a corresponding row of the memory. A K-wide FMAX( ) comparator has a first set of K-wide inputs of the K-wide FMAX( ) comparator coupled to a read port of the memory and a second set of K-wide inputs of the K-wide FMAX( ) comparator coupled to the input bus, and a set of K-wide outputs of the K-wide FMAX( ) comparator coupled to a write port of the memory. A tree of FMAX( ) comparators comprises an input and an output, the input of the tree coupled to the set of K-wide outputs of the K-wide FMAX( ) comparator and the output of the tree coupled to the output bus.

A semiconductor die includes manually designed full-custom logic circuits implemented at transistor level and performing digital computation without use of standard-cell libraries or automated synthesis. The die lacks bond pads, wire-bond terminals, or through-silicon vias and operates only when bonded to another die or carrier through dense hybrid-bonded or microbump conductive interconnects. In related embodiments, a system includes such a compute die and a peripheral die providing power, clock, and communication functions. The architecture enables pad-less full-custom compute dies operating solely through inter-die bonding for all external connectivity.

An analog-digital hybrid deep neural network computing device according to one embodiment includes a control unit, an analog processing unit, a digital processing unit, and a multi-channel bus, and in which the algorithm includes a plurality of layers for computation, and an analog MAC computation in an analog computing manner is performed for a first group of layers including one or more layers among the plurality of layers in the analog processing unit and a digital MAC computation in a digital computing manner is performed for a second group of layers, which is the remaining layers except for the first group of layers, in the digital processing unit.

The invention provides a method for determining a matrix formula by using a regression model based on formation drilling requirements, and relates to the technical field of digital calculation methods specially suitable for specific functions. According to the method, the matrix design accuracy and efficiency are improved and the experiment cost is greatly reduced through the function relation between the mass fractions of the four basic components and the bending strength and the formula of reversely solving the basic components on the basis of the formation drilling requirement; the matrix hardness and strength can be dynamically matched according to the formation characteristics, the problem that an existing matrix formula design is difficult to adapt to the formation drilling requirement is solved, and the method is suitable for designing the matrix formula based on the formation drilling requirement.

The present application belongs to the technical field of digital computing or data processing equipment or method specially applied to specific application, discloses a method for analyzing the jet flow of a flame gun, establishes a mathematical model and a discrete method for the jet flow of the flame gun, and performs jet flow analysis based on the model; the calculation domain of the jet flow of the flame gun comprises a nozzle part and a jet flow part, the width of the calculation domain below the nozzle of the flame gun is set to 1.5 m, and the width above the nozzle is set to 0.5 m; in the boundary conditions of the calculation domain, the nozzle inlet is set as a velocity inlet, the nozzle pipe boundary is set as a wall surface, the ground is also set as a wall surface, and other boundaries are set as pressure outlets; the Reynolds average method is adopted to model the turbulent flow; the k-ε model is adopted to construct a turbulent flow model, and a two-layer wall surface model is introduced; the VOF model is adopted as a multiphase flow model; and the finite volume method is adopted to disperse the control equations. The present application solves the problem that the jet flow of the flame gun can be conveniently analyzed by constructing a jet flow model of the flame gun.

1. Name of the designed product: calculator (DS-2815C). 2. Use of the designed product: for digital calculation. 3. Design points of the designed product: in shape. 4. Picture or photo best indicating the design points: perspective view.

A high-speed matrix computation circuit, relating to electronic technology. The present invention comprises M+N-1 addition modules and a predetermined number of macro computation modules. Each macro computation module comprises M row lines and N column lines which are equivalently and orthogonally arranged. Multipliers are arranged at intersections of the row lines and the column lines to form a multiplier array composed of M x N multipliers. A first input terminal of each multiplier is connected to the row line in which the multiplier is located, and a second input terminal thereof is connected to the column line in which the multiplier is located. M and N are predetermined natural numbers. U[M-x][N-y] is used to represent a multiplier at each position, and x and y are both integers and satisfy the following conditions: 0≤x≤M-1, and 0≤y≤N-1. Among the macro computation modules, an output terminal of a multiplier satisfying x+y=S is connected to an input terminal of an addition module having a serial number S. On the basis of serial numbers, output terminals of the addition modules are connected to different bit weight input terminals of a bit weight addition circuit in a one-to-one correspondence. The present invention greatly reduces the amount of digital computation.

The invention discloses an agent performance evaluation method based on heterogeneous multi-dimensional index system fusion, which comprises the following steps of: firstly, constructing a heterogeneous multi-dimensional evaluation index system according to an evaluation target, designing a test scheme according to the heterogeneous multi-dimensional evaluation index system, collecting test data, performing index measurement and score assignment based on the test data, and performing evaluation on the evaluation target; and finally, calculating an efficiency evaluation result based on an improved analytic hierarchy process. According to the scheme, the accuracy and comparability of an evaluation result can be improved through quantitative processing and standardized mapping of test conditions in combination with evaluation target association degree and coverage of multi-dimensional feature factors influencing index performance, dependence on historical training data is not needed, and system deployment cost and early-stage investment are effectively reduced; according to the scheme, an interpretable digital calculation process is adopted in the whole process, transparency and traceability of an evaluation result are ensured, the high-credibility verification requirement is met, comprehensive analysis of the efficiency of the intelligent agent is achieved through a multi-dimensional index weight distribution mechanism, and the method is particularly suitable for a multi-target comprehensive evaluation scene of a complex system.

The application is suitable for the field of digital calculation management technology improvement, and provides a manufacturing PFMEA management system based on Django, which comprises an engine module and a whole vehicle module.The engine module is used for recording data information of each component of the engine and storing the data information in data, and generating a data index to form a one-to-one mapping relationship with the number of each engine.The whole vehicle module is used for recording feature data information of related components of the whole vehicle and generating index information to be stored in a database, and forming a one-to-one mapping relationship between the indexed whole vehicle data information and the frame number.The old table data can be quickly and batch imported, and manual input time and effort are avoided.

The invention relates to a real-time vibration compensation device and method for a cold atom gravimeter. The device comprises a Raman laser, a rubidium atomic group, a reflector, an accelerometer, an optical phase-locked loop module, an analog-to-digital converter, a reference clock source, a heteronuclear FPGA, a direct frequency generation module and an upper computer. Two pairs of Raman lasers oppositely act on a rubidium atomic group in the vertical direction, the accelerometer and the reflector are in rigid connection, analog differential signals of the accelerometer enter the analog-digital converter, converted digital signals enter the heteronuclear FPGA for digital calculation, and the reference clock source serves as clock signals of the digital circuit. A signal calculated by the heteronuclear FPGA enters the direct frequency generation module and is output to the optical phase-locked loop to control the phase of the Raman laser, and the heteronuclear FPGA communicates with the upper computer through TCP connection. The vibration real-time compensation device for the cold atom gravimeter is fully digital, and has the advantages of large dynamic range, low noise and high-precision phase synchronization compensation capability.

The invention relates to a method for movement-training a movement of at least one body part of a patient, said body part being provided with an orthopaedic device, said method comprising the following steps: - generating, by means of an electronic computing unit, a digital graphical movement representation of the body part provided with the orthopaedic device depending on a target movement which the body part is supposed to carry out with the provided orthopaedic device, - detecting, by means of a detecting apparatus, a body part movement of the body part of the patient provided with the orthopaedic device, and - superimposing, by an augmented reality device, the generated digital graphical movement representation as an augmented reality onto the reality of the patient perceived in the patient's direction of view in such a manner that the superimposition of the graphical movement representation is positioned depending on the detected body part movement.

Arrangements for intelligent provisioning of quantum programs to quantum hardware are provided. In some aspects, a quantum program of a plurality of quantum programs to be executed on target quantum hardware may be received from a digital computing device. The quantum program may be scanned and optimized for minimum quantum bit (qubit) consumption using one or more machine learning models. Based on an accuracy requirement of a quantum program output, a criticality level of the quantum program may be identified. In addition, a qubit count associated with the quantum program, indicating a number of qubits used to perform quantum processing of the quantum program, may be identified. Based on the identified criticality level and qubit count, an allocation of qubits together with target quantum hardware may be assigned for deploying the quantum program. The target quantum hardware may ingest the quantum program and perform quantum processing of the quantum program.

The neuron Logic Gate Metal-Oxide-Semiconductor (νLGMOS) circuits to mimic neurons' “integrate-and-fire” behaviors in biological neural network system can be fabricated with industry Complementary Metal-Oxide Semiconductor (CMOS) logic process technology, with which digital computational circuits are fabricated. A processing system having analog νLGMOS circuits, conversion circuitry and digital circuits optimized for power and cost for varieties of applications can be then fabricated with the same CMOS logic process technology for IC chips. Meanwhile analog νLGMOS circuits inspired from biological neural network systems can be simulated, designed, and fabricated for IC chips for the applications of biomedical fields.

Disclosed is a method of operating a computing system. The method performed in the computing system having one or more processors and a memory storing one or more programs executed by the one or more processors, includes receiving one of a plurality of artificial neural network architectures as a backbone architecture, determining a structure of a DCIM (Digital Computing-in-Memory) macro based on the backbone architecture, generating an approximate addition candidate group of the DCIM macro based on a first algorithm, generating a heterogeneous approximate DCIM based on the structure of the DCIM macro and the approximate addition candidate group, and mapping channel-specific weights with respect to the heterogeneous approximate DCIM based on a second algorithm.

An electromagnetic transient dynamic process simulation system under a power grid fault based on new energy grid connection belongs to the technical field of new energy power generation, and is characterized in that mathematical models of power system elements are built on a digital calculation tool platform such as a computer, and then a network formed by the mathematical models is solved through various numerical algorithms. The digital simulation has the main advantages of being not limited by the simulation scale, short in modeling and debugging time, safe and reliable in test environment, low in test cost and the like. With continuous development of digital technologies such as computers, the digital simulation technology has become a simulation means mainly used in scientific research and test work of an electric power system. The simulation system adopts an implicit trapezoidal integral method and a transient equivalent circuit to solve a network, supports interaction among a new energy side control system, a power grid relay protection device and a power grid model, and realizes comprehensive simulation of the network, a motor and a secondary control system.

The present disclosure provides an analog-digital hybrid computing method and a neuromorphic system using the same. The neuromorphic system includes: an input signal section that generates an input signal; a synapse section that includes synapse units that receive the input signal and flow a current according to a set weight, each synapse unit including a storage unit that is provided in a memory array including an input electrode line and an output electrode line and generates an output signal; a digital computing section that digitizes and sums the output signals; and a control section that specifies a digitization bit number for each output electrode line and stores a logic state in the storage unit; causes the input signal to be applied to each storage unit of each synapse unit through each input electrode line; generates, for each output electrode line, a sum of the currents flowing from the storage units of each synapse unit by the input signal as an output signal; and causes the digital computing section to digitize the output signals according to the bit number and calculate a sum of the digitized output signals.

The invention provides an acceleration system and method of a random Fourier feature learning algorithm, relates to the technical field of hardware acceleration of the random Fourier feature learning algorithm, and realizes hardware native calculation of a random Fourier feature kernel function through light wave interference. Mathematical mapping and complex operation are converted into a continuous physical process of optical phase modulation and interference, and the analog-to-digital conversion and digital operation overhead of a traditional electronic architecture is reduced. The dynamic reconfigurable light modulation unit is combined with a wavelength multiplexing technology, supports real-time adjustment and multi-probability distribution switching of RFF kernel function parameters, and flexibly adapts to diversified data characteristics and task requirements. The system-level photoelectric hybrid interconnection and multi-modal scheduling mechanism realizes hierarchical expansion from vector inner product to matrix operation, an attention mechanism and a Transform model, and considers edge end low-power-consumption reasoning and a data center-level training scene. The anti-interference characteristic of optical calculation and the hardware-algorithm closed-loop calibration design guarantee the calculation precision and reliability in a complex environment.

A method of computing logarithms, comprising receiving a number, computing an exponent and significand of the received number, selecting a breakpoint value from a plurality of breakpoint values segmenting a range of the significand wherein the selected breakpoint value is the significand's greatest lower bound or lowest upper bound, computing a multiplication of the exponent and a logarithm value of two, computing a first intermediate value based on a least significant portion of the significand and an inverse value of the selected breakpoint value, computing an approximated logarithm value of a second intermediate value derived from the first intermediate value, computing a logarithm value of the significand by summing the approximated logarithm value and a logarithm value of the selected breakpoint value, computing a logarithm value of the received number by summing the logarithm value of the significand and the multiplication of the exponent and the logarithm value of two.

The disclosure relates to randomized sequences for row and / or column addressing. Computation weight data for in-memory computation operations is stored in memory cells of a memory array. During performing an in-memory compute operation, compute weight data is read from a memory array using a randomly selected row and / or column access order. The digital computation processing circuit receives the feature data for the computation operation in the memory and performs the computation operation according to the feature data and the read computation weight data. A mapping signal generated in response to a memory access provides information specifying an access order of random scrambling. When a computing operation for a computing operation in the memory is performed, the digital computing processing circuitry maps the retrieved computing weight data to the feature data using the information.