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Method for realizing high-parallel frame predicator

An intra-frame prediction and predictor technology, which is used in television, electrical components, digital video signal modification and other directions, can solve the problems of increasing control logic complexity, complexity and redundancy, and achieves reduction of circuit area and simplification. The effect of control logic

Inactive Publication Date: 2007-03-28
TSINGHUA UNIV
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AI Technical Summary

Problems solved by technology

3 kinds of prediction blocks of different sizes and up to 17 kinds of prediction modes, while improving the prediction accuracy, it also greatly increases the complexity and redundancy of hardware implementation
The reconfigurable method saves hardware resources at the cost of reducing the parallelism of calculations, and needs to schedule the input and output data of each computing unit, which increases the complexity of the control logic

Method used

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  • Method for realizing high-parallel frame predicator
  • Method for realizing high-parallel frame predicator
  • Method for realizing high-parallel frame predicator

Examples

Experimental program
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Embodiment Construction

[0173] Here is a detailed description of the specific implementation process of the adders module and the plane module after removing the calculation redundancy by using the digital calculation intensity reduction algorithm, and the implementation mode of the select module.

[0174] The adders module shown in Figure 6 is composed of an adder group. By observing the prediction formulas of mode 0 to mode 14 of 16 pixels in a 4×4 size block, the same addition operation is only calculated once and the result is shared. In order to reduce the length of the critical path, a set of registers is inserted between the 10-bit adder bank and the 11-bit adder bank of Figure 6. The addition operation completed by each adder group in Figure 6 is as follows:

[0175] 8bit adder group:

[0176] Numbering

[0177] 9bit adder group:

[0178] Numbering

[0179] 10bit adder group:

[0180] Numbering

[0181] 11bit adder group:

[0182] Numbering

[0...

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Abstract

The invention belongs to Video decoder IC design field. The character is in that: to the same operation among the prediction formulas in 17 different prediction modes of 4x4 block with 16 pixels adopting digit computation strength cut method to remove computation redundance; providing a in-frame predictor system with high degree of parallelism, which can process the predicted values of 16 pixels within every clock cycle. From the results achieved, compared to the design with the use of reconstruction, this invention can decrease circuit area under same parallelism and simplifies the control logic.

Description

technical field [0001] The invention relates to the field of integrated circuit design of video codec. Background technique [0002] The H.264 standard is a joint video group (JVT, Joint VideoTeam) of the VCEG (Video Coding Experts Group) of the ITU-T and the MPEG (Moving Picture Experts Group) of the International Organization for Standardization / International Electrotechnical Commission ISO / IEC. developed standard, which is the latest video coding standard. Similar to the previous standards, they all achieve the purpose of compression by removing the spatial and temporal redundancy of the image. [0003] Intra prediction in H.264: [0004] The intra prediction of H.264 is to use the adjacent pixels above and to the left of the current block as reference pixels to predict the pixels of the current block, effectively remove the spatial redundancy, and greatly improve the coding efficiency. For the luminance component, H.264 has two different sizes of blocks for intra pred...

Claims

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Application Information

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IPC IPC(8): H04N7/32H04N7/26H04N19/136H04N19/33H04N19/40H04N19/48H04N19/593H04N19/61
Inventor 李树国杨晨
Owner TSINGHUA UNIV
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