Accumulation circuit for floating-point numbers and realization method thereof

An accumulation circuit and floating-point number technology, applied in the field of digital computing, can solve the problem of low performance of floating-point number calculations, achieve the effect of reducing one-level addition operations, reducing one-level XOR operations, and shortening delays

Inactive Publication Date: 2012-11-28
HUAWEI TECH CO LTD
View PDF5 Cites 10 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Embodiments of the present invention provide a floating-point number accumulation circuit and its implementation method. By optimizing the timing of the critical calculation path of the calculation system, the problem of low floating-point calculation performance of the calculation system in the prior art is solved, and the improvement is improved. Computing performance of the computing system

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Accumulation circuit for floating-point numbers and realization method thereof
  • Accumulation circuit for floating-point numbers and realization method thereof
  • Accumulation circuit for floating-point numbers and realization method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0039] This embodiment provides a floating-point number accumulation circuit, such as figure 1 As shown, the circuit includes: a signal input terminal 101, an inversion circuit 102, an exponential operation circuit 103, a sign sum operation circuit 104, an order matching circuit 105, a two-way accumulation circuit 106, an addition circuit 107, a sign selection circuit 108, specifications circuit 109, overflow processing circuit 110 and signal output terminal 111, wherein,

[0040] The signal input terminal 101 is used to obtain a first floating-point number signal and a second floating-point number signal;

[0041] The inversion circuit 102 is used for inverting the first floating-point number signal and the second floating-point number signal;

[0042] The exponent operation circuit 103 is used to obtain a first power exponent according to the first floating-point number signal, obtain a second power exponent according to the second floating-point number signal, and obtain a...

Embodiment 2

[0054] This embodiment provides a floating-point number accumulation circuit, which inputs a floating-point number signal a and a floating-point number signal b from a signal input terminal, and outputs an accumulation result z at a signal output terminal, where z=a+b, such as figure 2 As shown, the circuit includes: a signal input terminal 101, an inversion circuit 102a, an inversion circuit 102b, an exponent operation circuit 103, a sign sum operation circuit 104, an order-to-order circuit 105a, an order-to-order circuit 105b, a two-way accumulation circuit 106, Adding circuit 107, symbol selection circuit 108a, symbol selection circuit 108b, normalization circuit 109, overflow processing circuit 110 and signal output terminal 111, wherein,

[0055] The signal input terminal 101 is used to obtain two floating-point number signals a and b.

[0056] Wherein, the floating-point number signal a may be a floating-point number signal or a sum signal of at least two floating-point...

Embodiment 3

[0075] This embodiment provides a method for implementing a floating-point number accumulation circuit, such as image 3 As shown, the method includes:

[0076] 301. Obtain a first floating-point number signal and a second floating-point number signal through a signal input terminal.

[0077] For example, the obtained floating-point signal can be two floating-point signal a and floating-point signal b, the output accumulation result is Z, and the operation process can be: Z=a+b, where b can be the product of multiple floating-point signals Signals, such as b=c×d, a can be the sum signal of multiple floating-point number signals, and this addition form is extended to general floating-point number operations:

[0078] where a i 、c j and d j Both are floating point signals, b j =c j × d j , i=0, 1, ..., n-1, j = 0, 1, ..., m-1, as long as from a i and b j In any group or two groups, two or more floating-point number signals can be combined, that is, n≥0, m≥0, and n+m≥2. ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The embodiment of the invention discloses an accumulation circuit for floating-point numbers and a realization method thereof, relating to the technical field of digital computation. The method comprises the following steps of: performing a negation operation, an exponent arithmetic operation, a symbol sum arithmetic operation, an exponent matching operation, a double-circuit accumulation operation, an addition operation, a symbol selection operation, a normalization operation, an overflow handling operation on at least two floating-point number signals, and outputting the accumulation result of the combination of the input signals. The accumulation circuit for floating-point numbers and the realization method for the same disclosed by the invention are suitable for floating-point number arithmetic.

Description

technical field [0001] The invention relates to the technical field of digital calculation, in particular to building a floating-point number accumulation circuit in a digital signal processor or a hardware accelerator system and its realization method. Background technique [0002] In recent years, the requirements for high precision and high dynamic range in applications in various fields have gradually become the most important link. Compared with fixed-point numbers, floating-point numbers have higher precision and higher dynamic range, so floating-point numbers are getting more and more attention. Floating-point numbers are used to approximate a real number, and its format can be expressed as {S,E,M}, where S is the sign, E is the exponent, and M is the normalized mantissa, for example, {S,E,M}= (-1) s ×(1+m)×2 e . Due to the characteristics of the floating-point number itself, the calculation of the floating-point number is more complicated, so to obtain the result...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/50
Inventor 程志坤
Owner HUAWEI TECH CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap