Complex multiplier

Abstract

The invention discloses a complex multiplier which comprises a data interface, a first partial product generating module, a second partial product generating module, a third partial product generatingmodule, a fourth partial product generating module, a first accumulator and a second accumulator, wherein the data interface comprises an input interface and an output interface; the first partial product generating module generates the partial product of real parts of two complex numbers; the second partial product generating module generates the negative value of the partial product of imaginary parts of the two complex numbers; the third partial product generating module generates the partial product of the real part of the first complex number and the imaginary part of the second complexnumber; and the fourth partial product generating module generates the partial product of the imaginary part of the first complex number and the real part of the second complex number. The invention reduces the area, lowers the power consumption, shortens the key path of the whole complex multiplier, and simplifies the computation, thereby improving the operating speed and the processing speed.

Description

【Technical field】 [0001] The invention relates to a complex number multiplier, and mainly relates to the field of digital signal processing such as baseband signal processing, radar, sonar, etc. that need to process complex number multiplication. 【Background technique】 [0002] In the field of real-time signal processing, for example, an FFT (Fast Fourier Transform, Fast Fourier Transform) circuit in an OFDM system often requires a complex multiplier. Existing straightforward implementations of complex multipliers such as figure 1 As shown, this complex multiplier requires four real multipliers, an adder, and a subtractor, as figure 2 As shown, its disadvantage is that the area is larger and the delay is longer. In the FFT processor, the way to accelerate the speed of the complex multiplier is to process the complex multiplier in a pipeline structure and divide it into two or more pipeline segments. However, due to the characteristics of the pipeline structure of the FFT ...

AI Technical Summary

Problems solved by technology

Existing straightforward implementations of complex multipliers such as figure 1 As shown, this complex multiplier requires four real multipliers, an adder, and a subtractor, as figure 2 As shown, the disadvantage is that the area is larger and the delay is longer

In the FFT processor, the way to accelerate the speed of the complex multiplier is to process the complex multiplier in a pipeline structure and divide it into two or more pipeline segments. However, due to the characteristics of the pipeline structure of the FFT processor, the existing complex multiplier After multi-stage pipeline processing, the hardware control complexity of the FFT processor is increased

Images