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Round transformation multiplexing circuit and AES (Advanced Encryption Standard) decryption circuit

A technology of multiplexing circuits and round transformation, which is used in electrical components, encryption devices with shift registers/memory, digital transmission systems, etc., to reduce the implementation area, improve the efficiency of circuit optimization, and reduce the implementation area.

Active Publication Date: 2018-11-13
ANHUI UNIVERSITY OF TECHNOLOGY AND SCIENCE
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The embodiment of the present invention provides an AES decryption circuit, which aims to solve the problem that the existing round transformation circuits based on merge operations optimize the length of the critical path at the cost of increasing the circuit area

Method used

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  • Round transformation multiplexing circuit and AES (Advanced Encryption Standard) decryption circuit
  • Round transformation multiplexing circuit and AES (Advanced Encryption Standard) decryption circuit
  • Round transformation multiplexing circuit and AES (Advanced Encryption Standard) decryption circuit

Examples

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Effect test

Embodiment 1

[0130] The decryption method of the AES decryption circuit provided by Embodiment 1 includes the following steps:

[0131] S1. The first 4 calculations constitute the first round of transformation. The first round of transformation refers to inputting the four groups of four-byte ciphertext data from the ciphertext data input port into the round transformation multiplexing circuit, and the selector S2 performs the round transformation multiplexing circuit operation. a vector of the first through fourth rows of the result Output to register 1, when register 1 stores 16 bytes of data, transfer the stored data to register 2;

[0132] S2, the 5th to 4N of the multiplexing wheel conversion circuit r The operation constitutes (N r -1) general wheel transformation, register 2 outputs 4 bytes of data each time to the feedback data input end of the wheel transformation multiplexing circuit, and through the operation of the wheel transformation multiplexing circuit, the selector S2 t...

Embodiment 2

[0137] The decryption method of the AES decryption circuit provided by the second embodiment comprises the following steps:

[0138] S1. The first two operations constitute the first round of transformation. The first round of transformation means that the four-byte ciphertext data is input into two round transformation multiplexing circuits from the ciphertext data input port respectively, and the selector S2 converts the operation result of the round transformation multiplexing circuit. A vector consisting of the first to fourth rows of Output to register 1, when register 1 stores 16 bytes of data, transfer the stored data to register 2;

[0139] S2, the 3rd to 2nd N of the multiplexing round conversion circuit r The composition of the operations (N r -1) Common round-to-round conversion, register 2 outputs two sets of 4-byte data each time, and transmits them to the feedback data input terminals of the two round-conversion multiplexing circuits respectively. After the op...

Embodiment 3

[0144] The decryption method of the AES decryption circuit provided by the third embodiment comprises the following steps:

[0145] S1. The first operation constitutes the first round of transformation. The first round of transformation means that four groups of four-byte ciphertext data are respectively input into four rounded transformation multiplexing circuits from the ciphertext data input port, and the selector S2 converts the round transformation multiplexing circuit. A vector consisting of the first row to the fourth row of the operation result output to the register;

[0146] S2, the second to N of the multiplexing round conversion circuit r The composition of the operations (N r -1) Ordinary round-to-round conversion, the register outputs four groups of 4-byte data each time, which are respectively transmitted to the feedback data input terminals of the four round-conversion multiplexing circuits. A vector composed of vectors from the fifth row to the eighth row ...

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Abstract

The invention relates to the technical field of a password circuit and provides a round transformation multiplexing circuit and an AES (Advanced Encryption Standard) decryption circuit. According to the round transformation multiplexing circuit provided by the invention, through combination and composite calculations of a constant matrix, all linear transformation calculations in an AES decryptionalgorithm are combined into two composite matrixes: a composite matrix delta(-tilde) and a composite matrix inverse-V(-tilde). A key path of the AES decryption circuit is reduced, and moreover, an AES decryption realization area is reduced.

Description

technical field [0001] The invention relates to the technical field of cipher circuits, in particular to a round transformation multiplexing circuit and an AES decryption circuit. Background technique [0002] AES (Advanced Encryption Standard, Advanced Encryption Standard) is a new generation of block symmetric cipher algorithm formulated by the National Institute of Standards and Technology in 2001 to replace the original DES (Data Encryption Standard, Data Encryption Standard). At present, the AES encryption algorithm has been adopted by many international standard organizations, and it is currently the most widely used block encryption algorithm. [0003] The data packet length of the AES encryption algorithm is 128 bits, and the key lengths are 128, 192 and 256 bits, which are called AES-128, AES-192, and AES-256 respectively. The AES algorithm is an iterative algorithm. Each iteration can be called a round transformation. The key length is different, and the number of...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L9/06
CPCH04L9/0631H04L2209/12H04L2209/122H04L2209/125
Inventor 张肖强郑辛星梁广俊王新航王磊孙忠先
Owner ANHUI UNIVERSITY OF TECHNOLOGY AND SCIENCE
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