3778 results about "Process rate" patented technology

The present invention relates to an enhanced sequential atomic layer deposition (ALD) technique suitable for deposition of barrier layers, adhesion layers, seed layers, low dielectric constant (low-k) films, high dielectric constant (high-k) films, and other conductive, semi-conductive, and non-conductive films. This is accomplished by 1) providing a non-thermal or non-pyrolytic means of triggering the deposition reaction; 2) providing a means of depositing a purer film of higher density at lower temperatures; and, 3) providing a faster and more efficient means of modulating the deposition sequence and hence the overall process rate resulting in an improved deposition method. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

The present invention relates to an enhanced sequential or non-sequential atomic layer deposition (ALD) apparatus and technique suitable for deposition of barrier layers, adhesion layers, seed layers, low dielectric constant (low-k) films, high dielectric constant (high-k) films, and other conductive, semi-conductive, and non-conductive films. This is accomplished by 1) providing a non-thermal or non-pyrolytic means of triggering the deposition reaction; 2) providing a means of depositing a purer film of higher density at lower temperatures; 3) providing a faster and more efficient means of modulating the deposition sequence and hence the overall process rate resulting in an improved deposition method; and, 4) providing a means of improved radical generation and delivery. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. [37 C.F.R. § 1.72(b)].

The present invention relates to an enhanced non-sequential atomic layer deposition (ALD) technique suitable for deposition of barrier layers, adhesion layers, seed layers, low dielectric constant (low-k) films, high dielectric constant (high-k) films, and other conductive, semi-conductive, and non-conductive films. This is accomplished by 1) providing a non-thermal or non-pyrolytic means of triggering the deposition reaction; 2) providing a means of depositing a purer film of higher density at lower temperatures; and, 3) providing a faster and more efficient means of modulating the deposition sequence and hence the overall process rate resulting in an improved deposition method.

The present invention relates to an enhanced sequential atomic layer deposition (ALD) technique suitable for deposition of barrier layers, adhesion layers, seed layers, low dielectric constant (low-k) films, high dielectric constant (high-k) films, and other conductive, semi-conductive, and non-conductive films. This is accomplished by 1) providing a non-thermal or non-pyrolytic means of triggering the deposition reaction; 2) providing a means of depositing a purer film of higher density at lower temperatures; and, 3) providing a faster and more efficient means of modulating the deposition sequence and hence the overall process rate resulting in an improved deposition method.

Methods and systems for processing financial market data using reconfigurable logic are disclosed. Various functional operations to be performed on the financial market data can be implemented in firmware pipelines to accelerate the speed of processing. Also, a combination of software logic and firmware logic can be used to efficiently control and manage the high speed flow of financial market data to and from the reconfigurable logic.

The present invention is generally directed to a computer security management system that integrates a firewall with an intrusion detection system (IDS). In other words, the firewall and IDS of the present invention can be designed to communicate process or status information and packets with one another. The present invention can facilitate centralized control of the firewall and the IDS and can increase the speed at which packets are passed between a secured computer network and an external network. Increased packet processing speed can be achieved in several ways. For example, the firewall and IDS can process packets in series, in parallel, and sometimes singularly when one of the components is not permitted to process a packet. Alternatively, singular processing can also be performed when one component is permitted to pass a packet to the secured computer network without checking with the other component.

Transesterification, esterification, and esterification-transesterification (both one-step and two-step) for producing biofuels. The process may be enhanced by one or more of the following: 1) applying microwave or RF energy; 2) passing reactants over a heterogeneous catalyst at sufficiently high velocity to achieve high shear conditions; 3) emulsifying reactants with a homogeneous catalyst; or 4) maintaining the reaction at a pressure at or above autogeneous pressure. Enhanced processes using one or more of these steps can result in higher process rates, higher conversion levels, or both.

Methods and systems for processing financial market data using reconfigurable logic are disclosed. Various functional operations to be performed on the financial market data can be implemented in firmware pipelines to accelerate the speed of processing. Also, a combination of software logic and firmware logic can be used to efficiently control and manage the high speed flow of financial market data to and from the reconfigurable logic.

The invention is a method and apparatus for improving image-processing applications. Embodiments of the invention provide methods for preserving computation results and offer intermediary computation steps to allow the processing of images at any location to take advantage of previously processed image areas. The preferred embodiment offers a method for building a median filter that significantly improves the processing speed over basic techniques. By building a histogram hierarchy, image data statistics are added and subtracted using a multiplicity of histograms from the histogram hierarchy, where each histogram describes an image area. Furthermore, a histogram hierarchy is built using multiple layers, each layer defining a level of statistical resolution.

An online social network is managed using one server for database management tasks and another server, preferably in a distributed configuration, for CPU-intensive computational tasks, such as finding a shortest path between two members or a degree of separation between two members. The additional server has a memory device containing relationship information between members of the online social network and carries out the CPU-intensive computational tasks using this memory device. With this configuration, the number of database lookups is decreased and processing speed is thereby increased.

An accelerated graphics processing subsystem that significantly increases the processing speed of computer graphics commands. The preferred embodiment of this invention presents a first-of-its-kind graphics processing subsystem that combines the processing power of multiple, off-the-shelf, video cards, each one having one or more graphic processor units. The video cards can be used without substantial modification. Under the preferred embodiment, each video card processes instructions for drawing a predetermined portion of the screen which is displayed to the user through a monitor or other visual output device. The invention harnesses the power of multiple video cards without suffering from the high bandwidth constraints affecting prior attempts at parallel graphics processing subsystems.

A device and a method are provided for increasing processing speed and for ensuring system security when an application or a driver is added. The device includes a first CPU group 10A that executes software 20A composed of basic processing 22 and an OS 21A; a second CPU group 10B that executes software 20B composed of additional processing 23 and OS 21B corresponding to the additional processing, inter-processor communication means 40, and 402 used for communication between the first CPU 10A and the second CPU 10B, and access control means 30 that controls access made by the second CPU 10B to a memory 50 and / or an input / output device 60.

In Internet and related networks, a method of and system for substitute use of the normal checksum field space in information processing (IP) datagram headers for obviating current processing time and addressing space limitations, involving replacing the current checksum usage in the checksum field with its attendant processing time with further source host and destination host addresses of lesser processing time, thereby increasing the address space for the network and decreasing the require header processing time, and / or providing space for autonomous system numbers, a higher layer protocol-based routing information (including of the MPLS type) or for Virtual Private Networks Indentifiers in the header.

Strategies are described for processing image information in a linear form to reduce the amount of artifacts (compared to processing the data in nonlinear form). Exemplary types of processing operations can include, scaling, compositing, alpha-blending, edge detection, and so forth. In a more specific implementation, strategies are described for processing image information that is: a) linear; b) in the RGB color space; c) high precision (e.g., provided by floating point representation); d) progressive; and e) full channel. Other improvements provide strategies for: a) processing image information in a pseudo-linear space to improve processing speed; b) implementing an improved error dispersion technique; c) dynamically calculating and applying filter kernels; d) producing pipeline code in an optimal manner; and e) implementing various processing tasks using novel pixel shader techniques.

The invention discloses a consensus method based on a cross-chain transaction, a device thereof and a storage medium. The cross-chain transaction is the transaction among a plurality of parallel chains. The plurality of parallel chains are connected with an interconnecting chain. The consensus method comprises the following steps of randomly determining a to-be-verified parallel chain in the plurality of parallel chains according to a preset parameter; confirming a cross-chain transaction which is initiated by the determined parallel chain, and performing broadcasting to the interconnecting chain for performing consensus verification. Therefore the consensus method, the device thereof and the storage medium have advantages of greatly reducing a cheating risk, improving safety in cross-chain transaction, greatly reducing calculation amount, improving processing speed in cross-chain transaction and supporting dynamic adding and quitting Internet by a block chain node.

A RAID control apparatus comprises at least a cache memory; an update information management table for storing update information; an update information storage unit for storing, in the update information management table, update information by detecting a data update; a reference value generation unit for generating a reference value expressing a load of a write back processing by using a Small Write method and a Read & Bandwidth Write method based on the update information; a write method determination unit for determining a write method according to the reference value and a write unit for carrying out a write processing, in order to provide a write back method for a RAID apparatus capable of improving a processing speed at the time of updating even in the case of including the processing of updating a part of data stripes.

A technique aimed to decrease the resource required for operations on a structured document, decrease the amount of a memory used, and increase the processing speed when the structured document is processed. Elements constituting a structured document to be converted are separated into key elements and nonkey elements, a new element given a predetermined tag name and a predetermined attribute name is created, tag name conversion is performed to create a tag name character string and describe the tag name character string as an attribute value corresponding to the predetermined attribute name in the new element, content conversion is performed to create a content character string including contents of the nonkey elements and describe the content character string as a content of the new element, and the key elements are described unchanged in a converted structured document. The method is applied to a system handling structured documents such as XML.

The invention relates to a computer-based method and system to facilitate quality control for manufactured assemblies based on computer aided design (CAD) files. The instant invention mitigates the problems encountered with large CAD files by decomposing each of such files into a multi-file format. A large CAD file is thereby broken-down into smaller files that organize the information contained in the larger file. The organization is performed in such a way that the information pertinent to the measurement process is segregated into a different smaller file than the information not needed to calculate measurements. Thus, the computer running the computation accesses a smaller file containing a higher percentage of required information. Additionally, assisting the user in coordinating a match-up between the physical surfaces being measured and the proper associated CAD model version of that surface further increases the handling speed. In particular, the instant invention uses selection regions for each surface. A selection region consists of the representation of a three-dimensional rectangle region just large enough to enclose each individual surface. A selection region indexes each surface. Thus, when a measurement point is taken, a list of surface regions is automatically scanned in order to determine which region contains that point. The corresponding distance of that measurement point to the surface is then calculated.

A method is provided for detecting road-side edges in a road segment using a light-based sensing system. Input range data is captured using the light-based sensing system. An elevation-based road segment is generated based on the captured input range data. The elevation-based road segment is processed by filtering techniques to identify the road segment candidate region and by pattern recognition techniques to determine whether the candidate region is a road segment. The input range data is also projected onto the ground plane for further validation. The line representation of the projected points are identified. The line representation of the candidate regions is compared to a simple road / road-edge model in the top-down view to determine whether the candidate region is a road segment with its edges. The proposed method provides fast processing speeds and reliable detection performance for both road and road-side edges simultaneously in the captured range data.

A method for backing up the data of a disk array system having network file server and storage area network functions easily and rapidly without using a route for data to be not backed up. Upon receipt of a backup request, a network file server module copies files on the disk array system's regular volumes to a backup volume. The network file server module then requests a storage area network module to copy the files to an external storage device. Finally, the storage area network module copies the current contents of the backup volume to the external storage device. The network file server module can limit the data to be backed up, thereby reducing the backup time requirements. The load on a LAN does not increase because the storage area network module acquires the data to be backed up. The processing speed increases thanks to backup load distribution within the disk array system.

The subject invention is directed to a method and system for selecting and purchasing media advertising in a user / server environment accessed through a Web site. The method includes accessing a server system through a Web site by an advertiser in which the advertiser provides information relating to buying criteria and customer data through a form on the Web page in order to select and purchase media advertising. The server system receives and processes the information in order to create at least one media advertising rate request. The server system transmits the rate request to at least one media outlet for processing. The media outlet processes the rate request and transmits the processed rate request to the server system. The server system manipulates the processed rate request to create a media advertising schedule and then transmits the advertising schedule to the advertiser. The advertiser receives the schedule, makes a media advertising purchase decision and transmits the purchase decision back to the server system. Thereafter, the server system transmits the media advertising purchase decision to the media outlet for reserving the purchased advertising.

Implementations of transforms, such as a discrete cosine transform (DCT) and inverse DCT on a graphics processing unit (GPU), use direct matrix multiplication. GPU features such as parallel graphics pipelines, multi-channel capability, and multiple render targets are used to obtain significantly faster processing speeds than on a conventional central processing unit (CPU). Various rendering modes may be used, such as point rendering mode, line rendering mode, and triangle or quadrilateral rendering mode.

In the invention, the detecting system comprises a video camera and a signal processor. It uses an improved Gaussian mixture distribution model to characterize each pixel in image frame; the characterized feature only uses a brightness feature; if there isn't a moving object (vehicle), the video image is relatively static; each pixel obeys a statistic model along with time variation; when getting a new image frame, the Gaussian mixture distribution model is renewed, if the pixel in current image match the Gaussian mixture distribution model, then determining the pixel is a background point; otherwise, determining the pixel is a foreground point.

Disclosed in the invention is a programmable visual chip-based visual image processing system, comprising an image sensor and a multilevel parallel digital processing circuit. The image sensor mainly includes a pixel array, an analog preprocessing circuit array and an analog-to-digital conversion circuit array; and the digital processing circuit consists of a parallel processing unit array with an M*M pixel level, a parallel processing unit array with M*1 rows, an on-chip artificial neural network and a reduced instruction processor dual-core subsystem. According to the provided system, high quality image collection with high speed and multilevel parallel image processing are realized and several high-speed intelligent visual application can be realized by programming; and compared with a traditional image system, the provided system has advantages of high speed, high integration, low power consumption and low cost. Moreover, the invention brings forward an embodiment for realizing the above-mentioned system as well as several high-speed intelligent visual image processing algorithms based on the embodiment. High-speed motion detection, high-speed gesture identification and rapid face detection are included; and the processing speed can reach 1000 frames per second. Therefore, a requirement of high-speed real-time processing can be met.

The present invention relates to a multithread processor. In the multithread processor, when a cache miss occurs on a request related to an instruction in, of a plurality of caches arranged hierarchically, a cache at the lowest place in the hierarchy, with respect to the request suffering the cache miss, a cache control unit notifies an instruction identifier and a thread identifier, which are related to the instruction, to a multithread control unit. When a cache miss occurs on an instruction to be next completed, the multithread control unit makes the switching between threads on the basis of the instruction identifier and thread identifier notified from the cache control unit. This enables effective thread switching, thus enhancing the processing speed.