24 results about "Interprocessor communication" patented technology

The invention discloses a communication method between graphics processors, a product, equipment and a medium, relates to the technical field of high-performance calculation and artificial intelligence acceleration, and is applied to a stand-alone system comprising a plurality of graphics processors and a central photoelectric hybrid switching chip constructed based on interconnection of an electric switching matrix and an optical switching matrix. The graphics processor is connected with the central photoelectric hybrid switching chip through an optical link and an electric link; the method comprises the following steps: performing data classification on to-be-transmitted data of a source graphics processor; if the to-be-transmitted data is a control flow, the source graphics processor is controlled to send the to-be-transmitted data to an electric switching matrix through an electric link, and then the to-be-transmitted data is routed to a target graphics processor in the graphics processors; and if the to-be-transmitted data is a data stream, the source graphics processor is controlled to send the to-be-transmitted data to the optical switching matrix through the optical link, and then the to-be-transmitted data is routed to the target graphics processor. Interconnection between graphics processors is optimized to improve communication efficiency between graphics processors.

A multi-processor communication framework (MCF) based on Transmission Control Protocol / Internet Protocol (TCP / IP) architecture is defined that can be used for inter-processor communication between heterogenous processing nodes. The MCF includes an application layer, a transport layer, a network layer, and an inter-processor communication (IPC) layer for each processing node. The IPC layer can be used to facilitate data transfer between two processing nodes via a physical channel within an electronic device, or through shared memory. The MCF can support multicast, broadcast, unicast, and zero-copy features like the TCP / IP stack.

A gateway (2) for a fieldbus system (100), wherein the gateway (2) comprises a first processor (6) with a first operating system (62), a second processor (7) with a second operating system (72) which is different from the first operating system (62) and has a virtual Ethernet interface (73), and an inter-processor communication interface (9) which is designed to enable an Ethernet protocol-based inter-process communication between the first operating system (62) and the second operating system (72) using the virtual Ethernet interface (73).

An apparatus for interprocessor communication includes a coupling element, a first transducer, and a second transducer. The coupling element includes a first interface to a first microprocessor and a second interface to a second microprocessor. The first interface and the second interface are connected together in a galvanically-isolated manner for communication purposes. The first transducer includes a third interface to the first microprocessor and a fourth interface to the second transducer. The second transducer includes a fifth interface to the second microprocessor and a sixth interface to the first transducer.

A radar sensor having at least one transmitting antenna and having at least one receiving antenna and having a radar SoC, the radar SoC comprising a radar generation circuit portion and a microcontroller circuit portion for the operation of the radar sensor and the processing of received radar data, characterized in that the radar SoC has an inter-processor communication interface and at least one further radar SoC having an inter-processor communication interface is provided, which communicates with the radar SoC via the inter-processor communication interface, wherein in the further radar SoC only the microcontroller circuit portion is functionally used for processing radar data, whereas the radar generation circuit portion is not functionally used.

The invention relates to a gateway (2) for a field bus system (100), wherein the gateway (2) comprises a first processor (6) with a first operating system (62), a second processor (7) with a second operating system (72) which is different from the first operating system (62) and has a virtual Ethernet interface (73), and an interprocess communication interface (9) which is designed to enable an Ethernet protocol-based interprocess communication between the first operating system (62) and the second operating system (72) using the virtual Ethernet interface (73).

This application proposes a method, system, and server for hot-updating server firmware, relating to the field of server maintenance. When applied to a BMC (Browser Control Center), the method includes: receiving a remote update command carrying target configuration data; responding to the remote update command, writing the target configuration data to a target non-volatile memory area associated with the MCP (Machine Processor) and decoupled from the BIOS mirror storage area; sending a reset command to the SCP (Processor Controller), which instructs the SCP to perform an independent reset on the MCP, which has an independent power domain, after detecting that the target configuration data has been written, so that the MCP restarts, loads the target configuration data from the target non-volatile memory area, and updates the firmware layer logic of the underlying hardware of the server system; and obtaining update status information returned by the MCP through an inter-processor communication channel. This solution can adjust the server's firmware configuration data or fix firmware layer security vulnerabilities without restarting the main server system.

Various embodiments include techniques for inter-processor communication. The techniques include generating a relaxed store message that comprises a first epoch number, incrementing a first counter associated with the first epoch number, and transmitting the relaxed store message to a first directory included in a cache.

This disclosure relates to various implementations an embedded computing system. The embedded computing system comprises a hardware accelerator (HWA) thread user and a second HWA thread user that creates and sends out message requests. The HWA thread user and the second HWA thread user is communication with a microcontroller (MCU) subsystem. The embedded computing system also comprises a first inter-processor communication (IPC) interface between the HWA thread user and the MCU subsystem and a second IPC interface between the second HWA thread user and the MCU subsystem, where the first IPC interface is isolated from the second IPC interface. The MCU subsystem is also in communication with a first domain specific HWA and a second domain specific HWA.

A signal processing device and a vehicle communication device including the same are disclosed. The signal processing device according to an embodiment of the present disclosure includes: a first processor to receive a first message including a sensor signal based on a first communication scheme and to process the received first message; a second processor to receive a second message including a communication message based on a second communication scheme and to process the received second message; and a shared memory to operate to transmit the first message or the second message between the first processor and the second processor, wherein the first processor or the second processor is configured to receive the first message or the second message stored in the shared memory based on an interrupt signal. Accordingly, latency may be reduced and high-speed data transmission may be performed during inter-processor communication.

A microprocessor-PLD hybrid architecture includes an IPC microprocessor and a PLD in signal communication with the IPC microprocessor via an IPC interface. The IPC microprocessor outputs a data read command to initiate a data read operation or a data write command. The PLD includes a plurality of PLD modules that store data and a bus controller. The bus controller communicates with the plurality of PLD modules via a plurality of PLD interfaces and is configured to sequentially execute a set of bus controller instructions. The bus controller reads data from a target PLD module from among the plurality of PLD modules in response to receiving the data read command, and transfers the data to the IPC microprocessor. The bus controller receives data from the IPC microprocessor and stores the data in a target PLD module from among the plurality of PLD modules in response to receiving the data write command.

This application discloses a spatial audio processing method, apparatus, storage medium, and computer program product, relating to the field of audio processing technology. The method is applied to a spatial audio device, which includes a main processor, an audio digital signal processor (ADSP), and a sensor hub. The method includes: transmitting audio stream data to be processed to the ADSP via the main processor; transmitting head motion sensor data to the ADSP via the sensor hub using a preset inter-processor communication method; converting the head motion sensor data into head posture data via the ADSP; and performing spatial audio rendering processing on the audio stream data to be processed based on the head posture data to obtain and output spatial audio stream data. This application reduces the transmission latency of head motion sensor data in spatial audio devices, improves the real-time performance of spatial audio rendering processing, and enhances the actual effect of spatial audio.

A signal processing device and a vehicle communication device including the same are disclosed. The signal processing device according to an embodiment of the present disclosure includes: a first processor configured to receive a first message including a sensor signal in a vehicle based on a first communication scheme; a second processor configured to receive a second message including a communication message received from an external source based on a second communication scheme; and a shared memory configured to operate to transmit the first message or the second message between the first processor and the second processor. Accordingly, it is possible to reduce latency and to perform high-speed data transmission during inter-processor communication.

The invention discloses a spatial audio processing method and device, a storage medium and a computer program product, and relates to the technical field of audio processing, the method is applied to a spatial audio device, and the spatial audio device comprises a main processor, an audio digital signal processor and a sensor hub. The method comprises the following steps: transmitting to-be-processed audio stream data to an audio digital signal processor through a main processor; head motion sensor data are transmitted to an audio digital signal processor through a sensor hub in a preset inter-processor communication mode; and converting the head motion sensor data into head posture data through an audio digital signal processor, and performing spatial audio rendering processing on the to-be-processed audio stream data according to the head posture data to obtain spatial audio stream data and outputting the spatial audio stream data. According to the method and the device, the transmission delay of the head motion sensor data in the spatial audio equipment is reduced, the real-time performance of spatial audio rendering processing is improved, and the actual effect of spatial audio is improved.

This disclosure relates to various implementations an embedded computing system. The embedded computing system comprises a hardware accelerator (HWA) thread user and a second HWA thread user that creates and sends out message requests. The HWA thread user and the second HWA thread user is communication with a microcontroller (MCU) subsystem. The embedded computing system also comprises a first inter-processor communication (IPC) interface between the HWA thread user and the MCU subsystem and a second IPC interface between the second HWA thread user and the MCU subsystem, where the first IPC interface is isolated from the second IPC interface. The MCU subsystem is also in communication with a first domain specific HWA and a second domain specific HWA.

The invention provides a session keep-alive detection method and device for a distributed system. The method comprises the following steps: each interface board receives BGP session information of a BGP peer of a distributed system synchronized by a main control board through an inter-processor communication IPC channel serving as an inter-board communication channel; wherein the BGP peer IP address at least comprises the BGP peer IP address and the maximum keep-alive time; each interface board establishes a BGP session table entry to record the maximum keep-alive time corresponding to the BGP peer IP address, a packet receiving counter and a packet sending counter are set for the BGP session table entry record, and first period flag bits are set for the packet receiving counter and the packet sending counter respectively; and when any interface board finds the BGP session table item of the board based on the received peer BGP keep-alive message, resetting the count value of the packet receiving counter of the board and clearing the first period flag bit.

Various embodiments include techniques for performing self-synchronizing remote memory operations in a multiprocessor computing system. During a remote memory operation in the multiprocessor computing system, a source processing unit transmits multiple segments of data to a destination processing. For each segment of data, the source processing unit transmits a remote memory operation to the destination processing unit that includes associated metadata that identifies the memory location of a corresponding synchronization object. The remote memory operation along with the metadata is transmitted as a single unit to the destination processing unit. The destination processing unit splits the operation into the remote memory operation and the memory synchronization operation. As a result, the source processing unit avoids the need to perform a separate memory synchronization operation, thereby reducing inter-processor communications and increasing performance of remote memory operations.

Various implementations incorporate techniques for interprocessor communication. These techniques include generating a relaxed store message containing a first epoch number, incrementing a first counter associated with the first epoch number, and transferring the relaxed store message to a first directory contained in a cache.

The application discloses an inter-graphic processor communication method, product, device and medium, relates to the field of high-performance computing and artificial intelligence acceleration technology, and is applied to a single computer system comprising multiple graphic processors and a central optoelectronic hybrid switching chip interconnected based on an electrical switching matrix and an optical switching matrix. The graphic processors are connected with the central optoelectronic hybrid switching chip through optical links and electrical links. The method comprises the following steps: performing data type division on to-be-transmitted data of a source graphic processor; if the to-be-transmitted data is a control flow, controlling the source graphic processor to send the to-be-transmitted data to the electrical switching matrix through the electrical link, and then routing the to-be-transmitted data to a destination graphic processor in each graphic processor; if the to-be-transmitted data is a data flow, controlling the source graphic processor to send the to-be-transmitted data to the optical switching matrix through the optical link, and then routing the to-be-transmitted data to the destination graphic processor. The interconnection between the graphic processors is optimized to improve the inter-graphic processor communication efficiency.

A signal processing device and a vehicle communication device including the same are disclosed. The signal processing device according to an embodiment of the present disclosure includes: a first processor configured to receive a first message including a sensor signal in a vehicle based on a first communication scheme; a second processor configured to receive a second message including a communication message received from an external source based on a second communication scheme; and a shared memory configured to operate to transmit the first message or the second message between the first processor and the second processor. Accordingly, it is possible to reduce latency and to perform high-speed data transmission during inter-processor communication.

Various embodiments include techniques for performing self-synchronizing remote memory operations in a multiprocessor computing system. During a remote memory operation in the multiprocessor computing system, a source processing unit transmits multiple segments of data to a destination processing. For each segment of data, the source processing unit transmits a remote memory operation to the destination processing unit that includes associated metadata that identifies the memory location of a corresponding synchronization object. The remote memory operation along with the metadata is transmitted as a single unit to the destination processing unit. The destination processing unit splits the operation into the remote memory operation and the memory synchronization operation. As a result, the source processing unit avoids the need to perform a separate memory synchronization operation, thereby reducing inter-processor communications and increasing performance of remote memory operations.

Various embodiments include techniques for inter-processor communication. The techniques include generating a relaxed store message that comprises a first epoch number, incrementing a first counter associated with the first epoch number, and transmitting the relaxed store message to a first directory included in a cache.

The invention discloses an integrated circuit and a communication method between processors thereof, and relates to the technical field of integrated circuits. The method comprises the following steps: determining a first identifier respectively corresponding to a first processor and a second identifier respectively corresponding to a second processor; determining an access relationship between the first processor and the second processor; based on the access relationship, determining a matching relationship between a third identifier of the first processor and the first identifier, and a matching relationship between a fourth identifier of the second processor and the second identifier; and determining a communication state between the first processor and the second processor based on the matching relationship. According to the technical scheme, the communication security between the processors of the integrated circuit can be improved, the problem of communication information leakage is avoided, and thus the reliability of the integrated circuit can be improved.