19 results about "Transaction layer packet" patented technology

To reduce bandwidth overheads associated with a message authentication code (MAC), aggregation is useful. To ensure there is no latency impact, something more than aggregation is needed. Integrity and Data Encryption (IDE) securing transaction layer packets (TLPs) can be used in a dynamic manner whereby before aggregating a new packet to the IDE TLP, a determination is made regarding whether the packet contains user data so that the packets with user data can be sent immediately rather than wanting for more packets to aggregate. On the receiving side, execution of the packet can occur before completing an integrity check that occurs in IDE TLP transfers to reduce latency.

The present application relates to a dynamic self-adaptive virtual channel mapping method and apparatus, and a storage medium. The method includes: monitoring equivalent data flows of transaction layer packets of different transmit classes, and obtaining the sum of the equivalent data flows of all the transmit classes, the equivalent data flow being the product of a data length of the transaction layer packet and a coefficient; obtaining a pre-calculation value of the number of virtual channels corresponding to each transmit class base on the sum of the equivalent data flows of the transmit classes; and adjusting mapping from the transmit classes to the virtual channels according to the pre-calculation value to obtain a mapping relationship table from the transmit classes to the virtual channels.

This disclosure provides a high-speed peripheral component interconnect (PCIe) interface device and a method of operating the same. The PCIe interface device may include a performance analyzer and a traffic level controller. The performance analyzer may be configured to measure the throughput of multiple functions operating on one or more direct memory access (DMA) devices. The traffic level controller may be configured to assign traffic level values ​​to transaction layer packets received from the multiple functions based on their throughput.

A system and method for achieving peripheral component interconnect express (PCIe) redundancy and recovery are disclosed. In some embodiments, the system comprises an accelerated compute fabric (ACF) comprising a PCIe switch, an application host communicatively coupled to the ACF using one or more upstream PCIe links, and an endpoint device communicatively coupled to the ACF using one or more downstream PCIe links. The application host is configured to send PCIe transaction layer packets (TLP) addressed to the ghosted endpoint devices through the one or more upstream PCIe links, and the ACF is configured to redirect the PCIe TLP packets to the endpoint device through the one or more downstream PCIe links.

Modern datacenters require efficient mechanisms for memory resource sharing and utilization across distributed computing environments. Some of the disclosed embodiments introduce systems and methods incorporating a Resource Provisioning Unit (RPU) that performs host-to-host physical address translations, enabling external hosts to access memory resources utilizing CXL protocols. The system includes a processor coupled to DRAM, an MMU for virtual-to-physical address mapping, and a CXL device for host communication. The RPU enables hosts to access the DRAM utilizing messages conforming to CXL protocols, including CXL.mem with Host-managed Device Memory (HDM) regions and CXL.io with Transaction Layer Packets. Some embodiments support multiple hosts and CXL memory expanders utilizing additional CXL devices and root ports. The embodiments enable flexible memory architecture, improved resource utilization, and scalable memory sharing suitable for AI workloads, cloud computing, and next-generation datacenter deployments.

The invention discloses an order preserving method and device, electronic equipment and a storage medium, and belongs to the technical field of computers. The method comprises the steps that transaction layer packets are received, corresponding authorization indication signals are generated, the authorization indication signals are used for representing the receiving time sequence of the corresponding transaction layer packets, the transaction layer packets are divided into first-class packets and second-class packets, the first-class packets are used for achieving one-way data issuing, and the second-class packets are used for achieving two-way data interaction; based on the authorization indication signal of each transaction layer packet, recording the number of preposed first-class packets associated with each second-class packet, the authorization indication signal of the preposed first-class packet being generated before the second-class packet; and for the processed second type of packets, when the number of the preposed first type of packets associated with the second type of packets is zero, sending the second type of packets. According to the scheme, the number of the front packets is counted by adopting the authorization indication signal, and the order preservation is realized according to the judgment on whether the number of the front packets returns to zero or not, so that additional parameters do not need to be processed along with a pipeline, and the hardware resource overhead is reduced.

The invention provides a PCIe (Peripheral Component Interconnect Express) dynamic bandwidth allocation and low-delay communication method and system based on an FPGA (Field Programmable Gate Array), and the method comprises the steps: carrying out the real-time statistics of the data transmission quantity of a plurality of virtual channels, and obtaining the flow data of the plurality of virtual channels; dynamically allocating bandwidth weights of the plurality of virtual channels according to the traffic data of the plurality of virtual channels to obtain credit values of the plurality of virtual channels; according to the credit values of the plurality of virtual channels, controlling the data transmission burst amount of the plurality of virtual channels, and performing hardware unloading processing on a transaction layer data packet received by the PCIe interface through a transaction layer packet analysis operation to obtain target address information and a data load; according to the target address information, the data load is directly written into an internal storage area of the FPGA through memory mapping operation, and transmission completion data is obtained. The method and the device can adapt to sudden data transmission requirements, and the bandwidth utilization rate is improved.

Systems, methods, and apparatus related to shared work queue interfaces for memory devices. In one approach, an NVMe solid-state drive (SSD) includes NAND flash memory. A controller of a host system writes an NVMe command to the SSD using a PCIe transaction layer packet. The command is written using either a deferred memory write or a memory write according to the PCIe standard. The command is written to the SSD either directly or via a local shared work queue of the host system.

This application provides a PCIe packet conversion method, system, medium, and device, relating to the field of computer hardware technology. The method includes: upon receiving a transaction layer packet, determining the packet source of the transaction layer packet, and then performing corresponding routing conversion operations based on the packet source and access address. This enables parallel design of multiple non-transparent bridges under the PCIe protocol, supporting communication between upstream devices in different PCIe domains through non-transparent bridges within their respective PCIe domains, supporting communication between downstream devices in different PCIe domains through non-transparent bridges within their respective PCIe domains, and supporting communication between upstream devices in one PCIe domain and downstream devices in other PCIe domains through non-transparent bridges within their respective PCIe domains. This eliminates the need for external wiring between different partitions on the same PCIe switch, supports parallel connections between different partitions on the same PCIe switch, and enables flexible access between devices in different PCIe domains.

Systems, methods, and apparatus related to shared work queue interfaces for memory devices. In one approach, an NVMe solid-state drive (SSD) includes NAND flash memory. A controller of a host system writes an NVMe command to the SSD using a PCIe transaction layer packet. The command is written using either a deferred memory write or a memory write according to the PCIe standard. The command is written to the SSD either directly or via a local shared work queue of the host system.

To reduce the bandwidth overhead associated with a message authentication code (MAC), aggregation is beneficial. However, to ensure no latency impact, more than just aggregation is required. Integrity and Data Encryption (IDE) can be dynamically employed to secure transaction layer packets (TLPs). This determines whether a new packet contains user data before aggregating it into an IDE-TLP, allowing packets containing user data to be sent immediately instead of requiring further packet aggregation. On the receiving end, packet execution can occur before the integrity check performed during IDE-TLP transmissions is completed, further reducing latency.

The invention relates to source ordering in device interconnects. In one embodiment, an apparatus includes a port to transmit and receive data over a link; and a protocol stack circuit to implement one or more layers of a load-store input / output (I / O) based protocol (e.g., PCIe or CXL) across links. The protocol stack circuitry builds a memory write request transaction layer packet (TLP) for the memory write transaction, where a field of the memory write request TLP indicates a virtual channel (VC) other than the VC0, responsive to the memory write transaction requiring completion, and a flow identifier associated with the memory write transaction. The memory write request TLP is sent on the link and in response a completion TLP is received on the link, the completion TLP indicating completion of the memory write request TLP.

In order to reduce bandwidth overhead associated with a message authentication code (MAC), aggregation is useful. In order to ensure that there is no delay effect, more measures need to be taken in addition to aggregation. An integrity and data encryption (IDE) secure transaction layer packet (TLP) may be used in a dynamic manner, thereby determining whether a new packet contains user data prior to aggregating the packet to the IDE TLP, such that packets with user data may be sent immediately, rather than desiring to aggregate more packets. At the receive side, packets may be performed to reduce latency prior to completion of an integrity check occurring in IDE TLP transmissions.

A system for sharing peripheral component interconnect express (PCIe) devices across multiple host servers is disclosed. In some embodiments, a switch includes a plurality of hosts associated with a plurality of hierarchies, one or more endpoints associated with one or more of the plurality of hierarchies, and a switch communicatively connectable to the plurality of hosts and the one or more endpoints. The switch is configured to: receive a transaction layer packet (TLP); determine a policy group identifier based on parsing and processing the TLP; perform packet forward matching based on the policy group identifier and destination fields of the TLP; based on whether the TLP is communicated between the hosts and endpoints in different hierarchies of the plurality of hierarchies, determine whether to edit the TLP using one or more rewrite rules; and forward the TLP to an appropriate destination link.

Systems, methods, and apparatus related to shared work queue interfaces for memory systems. In one approach, an NVMe solid-state drive (SSD) includes NAND flash memory. A controller of a host system writes NVMe commands to the SSD using a PCIe transaction layer packet. The host system can selectively configure a shared work queue interface of the SSD. A host / processor sends a get feature command to determine whether an SWQ interface is supported by the SSD. If the SSD supports the SWQ interface, then the SSD provides a response that identifies the resources provided by an NVMe controller in the SSD for use of the SWQ feature. The host / processor can send a command to enable / disable the SWQ feature using a set feature command. A queue pair can also be used whether the SWQ feature is enabled or disabled.

Modern datacenters require efficient mechanisms for memory resource sharing and utilization across distributed computing environments. Some of the disclosed embodiments introduce systems and methods incorporating a Resource Provisioning Unit (RPU) that performs host-to-host physical address translations, enabling external hosts to access memory resources utilizing CXL protocols. The system includes a processor coupled to DRAM, an MMU for virtual-to-physical address mapping, and a CXL device for host communication. The RPU enables hosts to access the DRAM utilizing messages conforming to CXL protocols, including CXL.mem with Host-managed Device Memory (HDM) regions and CXL.io with Transaction Layer Packets. Some embodiments support multiple hosts and CXL memory expanders utilizing additional CXL devices and root ports. The embodiments enable flexible memory architecture, improved resource utilization, and scalable memory sharing suitable for AI workloads, cloud computing, and next-generation datacenter deployments.

Systems, methods, and apparatus related to shared work queue interfaces for memory systems. In one approach, an NVMe solid-state drive (SSD) includes NAND flash memory. A controller of a host system writes NVMe commands to the SSD using a PCIe transaction layer packet. The host system can selectively configure a shared work queue interface of the SSD. A host / processor sends a get feature command to determine whether an SWQ interface is supported by the SSD. If the SSD supports the SWQ interface, then the SSD provides a response that identifies the resources provided by an NVMe controller in the SSD for use of the SWQ feature. The host / processor can send a command to enable / disable the SWQ feature using a set feature command. A queue pair can also be used whether the SWQ feature is enabled or disabled.