56 results about "Transaction layer packet" patented technology

A fault-tolerant RAID system is disclosed. The system includes redundant RAID controllers coupled by a PCI-Express link. When a PCI-Express controller of one of the RAID controllers receives a PCI-Express memory write request transaction layer packet (TLP), it interprets a predetermined bit in the header as an interrupt request flag, rather than as its standard function specified by the PCI-Express specification. If the flag is set, the PCI-Express controller interrupts the processor after storing the message in the payload at the specified memory location. In one embodiment, an unused upper address bit in the header is used as the interrupt request flag. Additionally, unused predetermined bits in the TLP header are used as a message tag to indicate one of a plurality of message buffers on the receiving RAID controller into which the message has been written. The PCI-Express controller sets a corresponding bit in a register to indicate which message buffer was written.

An apparatus and method for sharing I / O devices. The apparatus has a first plurality of I / O ports, a second I / O port, and core logic. The first plurality is coupled to a plurality of operating system domains through a load-store fabric. Each of the first plurality routes transactions between the operating system domains and the switching apparatus. The second I / O port is coupled to a first shared input / output endpoint. The first shared input / output endpoint requests / completes transactions for each of the plurality of operating system domains. The core logic is coupled to the first plurality of I / O ports and the second I / O port. The core logic routes the transactions between the first plurality of I / O ports and the second I / O port and associates each of the transactions with a corresponding one of the plurality of operating system domains (OSDs) by encapsulating an OS domain header within a transaction layer packet.

A method enabling I / O devices to be shared among multiple operating system domains, including first communicating with each of the operating system domains according to a protocol that provides exclusively for a single system domain ithin the load-store fabric; and second communicating with the shared I / O endpoint according to a variant of the protocol to enable the shared I / O endpoint to associate a prescribed operation with a corresponding one of the independent operating system domains. The second communicating includes encapsulating an OS domain header within a transaction layer packet that otherwise comports with the protocol, wherein the value of the OS domain header designates the corresponding one of the operating system domains; and via core logic within a swithching apparatus, mapping the independent operating system domains to the shared I / O endpoint.

Device, system and method of modification of PCI Express packet digest. For example, an apparatus includes a credit-based flow control interconnect device to generate a credit-based flow control interconnect Transaction Layer Packet in which one or more bits of a digest portion carry non-ECRC data.

The present invention is a method for providing address decode and Virtual Function (VF) migration support in a Peripheral Component Interconnect Express (PCIE) multi-root Input / Output Virtualization (IOV) environment. The method may include receiving a Transaction Layer Packet (TLP) from the PCIE multi-root IOV environment. The method may further include comparing a destination address of the TLP with a plurality of base address values stored in a Content Addressable Memory (CAM), each base address value being associated with a Virtual Function (VF), each VF being associated with a Physical Function (PF). The method may further include when a base address value included in the plurality of base address values matches the destination address of the TLP, providing the matching base address value to the PCIE multi-root IOV environment by outputting from the CAM the matching base address value. The method may further include constructing a requestor ID for the VF associated with the matching base address value, the requestor ID being based upon the output matching base address value and a bus number for a PF which owns the CAM.

An I / O device includes a host interface coupled to a plurality of hardware resources. The host interface includes a transaction layer packet (TLP) processing unit that may receive and process a plurality of transaction layer packets sent by a plurality of processing units. Each processing unit may correspond to a respective root complex. The TLP processing unit may identify a transaction type and a processing unit corresponding to each transaction layer packet and store each transaction layer packet within a storage according to the transaction type and the processing unit. The TLP processing unit may select one or more transaction layer packets from the storage for process scheduling based upon a set of fairness criteria using an arbitration scheme. The TLP processing unit may further select and dispatch transaction layer packets for processing by downstream application hardware based upon additional criteria.

Embodiments of the present disclosure generally relate to a storage device with reduced latency and a method of accessing data by a storage device with reduced latency. In one embodiment, a method of accessing data by a storage device with reduced latency include triggering a controller of the storage device for issuing a host read request. The controller determines if latency is critical for completion of the host read request. The controller issues the host read request in dynamic host read request size if latency is critical.

A method of operation of a storage controller system includes: accessing a first controller having a synchronization bus; accessing a second controller, by the first controller, through the synchronization bus; and receiving a first transaction layer packet by the first controller including performing a multi-cast transmission between the first controller and the second controller through the synchronization bus.

The invention provides a system and method for identifying and communicating congested paths throughout a network fabric. Briefly, the present invention augments the congestion management mechanism defined in ASI to allow for the communication of congested paths through the fabric, rather than the simple congested output port notification supported today through the use of DLLPs. Further, it also uses the communication mechanisms already defined in the ASI specification to implement this additional capability. Specifically, the present invention uses Transaction Layer Packets (TLPs) to communicate the information concerning congested flows throughout the network. This packet type allows the inclusion of much more information than DLLPs, allowing a more comprehensive and elegant solution to the issue of congestion management in an Advanced Switching network fabric.