56 results about "Transaction layer packet" patented technology

Device, system and method of modification of PCI Express packet digest. For example, an apparatus includes a credit-based flow control interconnect device to generate a credit-based flow control interconnect Transaction Layer Packet in which one or more bits of a digest portion carry non-ECRC data.

The present invention is a method for providing address decode and Virtual Function (VF) migration support in a Peripheral Component Interconnect Express (PCIE) multi-root Input / Output Virtualization (IOV) environment. The method may include receiving a Transaction Layer Packet (TLP) from the PCIE multi-root IOV environment. The method may further include comparing a destination address of the TLP with a plurality of base address values stored in a Content Addressable Memory (CAM), each base address value being associated with a Virtual Function (VF), each VF being associated with a Physical Function (PF). The method may further include when a base address value included in the plurality of base address values matches the destination address of the TLP, providing the matching base address value to the PCIE multi-root IOV environment by outputting from the CAM the matching base address value. The method may further include constructing a requestor ID for the VF associated with the matching base address value, the requestor ID being based upon the output matching base address value and a bus number for a PF which owns the CAM.

Embodiments of the present disclosure generally relate to a storage device with reduced latency and a method of accessing data by a storage device with reduced latency. In one embodiment, a method of accessing data by a storage device with reduced latency include triggering a controller of the storage device for issuing a host read request. The controller determines if latency is critical for completion of the host read request. The controller issues the host read request in dynamic host read request size if latency is critical.