36 results about "Shift-and-add" patented technology

The present invention comprises a method for through the wall radar imaging. An impulse synthetic aperture radar system transmits short, ultra-wideband carrierless microwave pulses at an obstacle behind which a target of interest is located. The return signals are received, stored and analyzed. Portions of the return signals that represent reflections from the obstacle are identified and analyzed in the time domain to estimate the transmission coefficient of the wall, either by estimating wall parameters or by using a novel shift and add procedure. The estimated transmission coefficient is used to filter the received signals to reduce the components of the received signal that are generated by the obstacle, and to compensate for distortion caused by the obstacle in the portions of the transmitted signal that are reflected by the target and returned, through the obstacle, to the radar system.

This invention relates to the design and implementation of a large family of fast, efficient, hardware-friendly fixed-point multiplierless inverse discrete cosine transforms (IDCT) and the corresponding forward transform counterparts. All of the proposed structures comprises of butterflies and dyadic-rational lifting steps that can be implemented using only shift-and-add operations. The approach also allows the computational scalability with different accuracy-versus-complexity trade-offs. Furthermore, the lifting construction allows a simple construction of the corresponding multiplierless forward DCT, providing bit-exact reconstruction if properly pairing with our proposed IDCT. With appropriately-chosen parameters, all of the disclosed structures can easily pass IEEE-1180 test. The high-accuracy algorithm of the present invention is over 100 times more accurate than IEEE-1180 specifications, leading to practically drifting-free reconstruction in popular MPEG-2 and MPEG-4 codecs even at the lowest quantization setting.

This invention relates to signal process arithmetic coding field and relates to image or video coding method, which is characterized by the following: designing new small possibility quantity scheme and the coding range and uses the displacement and adding technique to reduce the possibility of the complexity.

The invention belongs to the digital signal processing field, and specifically relates to a convolution calculating apparatus and method for a neural network. The convolution calculating apparatus andmethod for a neural network aims at solving the problem that consumption of resources is great and the utilization rate of the read in data is low during the process of convolution calculation. The convolution calculating method for a neural network includes the steps: input data matrixes are processed in rows, and every two rows of data are input serially row by row into multiply accumulator arrays for carrying out multiply and accumulate operations; the multiply accumulator arrays perform deployment according to a convolution kernel dimension (M2, N2), and can process 2*M2*N2 times of multiplication in parallel; and by means of the convolution operation law, the two groups of multiply accumulator arrays can be shifted and added, and the data operation is accelerated. The convolution calculating apparatus and method for a neural network can excavate parallelism during the calculating process and improve the calculating efficiency of the system, and at the same time can reuse the input data and directly put the calculation results into a pooling unit, thus being able to reduce data reading and writing. Besides, the convolution calculating apparatus and method for a neural networkonly need one row cushion space, thus having a small demand for resources, can realize calculation of different dimension convolution, and have the advantages of calculating flexibility, universality,high effectiveness and low power consumption property.

The invention discloses a method and a device for reconstructing a GPU (Graphic Processing Unit) accelerating X-ray image based on a CUDA (Compute Unified Device Architecture). The method comprises the following steps: transmitting acquired X-ray image projection data into a CPU (Central Processing Unit) memory by virtue of a CPU; partitioning the X-ray image projection data into multiple projection data regions by virtue of GPU, partially overlapping the adjacent projection data regions, and sending the multiple projection regions to the CPU memory; performing tomographic reconstruction on each projection data region by virtue of a GPU parallel kernel function accelerating shift and add algorithm, so as to obtain corresponding partial reconstruction images; splicing and synthesizing the partial reconstruction images into the reconstruction image. According to the method and the device, the parallel shift and add algorithm is realized by virtue of GPU hardware acceleration under the CUDA, so that the computing speed is greatly improved, meanwhile the cost is saved, and great convenience is brought to a user.

A frequency translator uses a CORDIC phase rotator coupled to a phase accumulator to translate an input signal in frequency. The CORDIC phase rotator performs required phase angle rotations of input vectors using only shift and add operations. Thus, the frequency translator can be readily implemented in hardware. Higher precision arithmetic is used in the CORDIC phase rotator operations than the input vectors contain. To avoid truncation error at the output of the CORDIC phase rotator, stochastic rounding is employed. A dither signal is added to avoid errors due to nonlinear operation of D/A converters, where D/A conversion of the frequency translated signal is required.

A mechanism implemented by a controller enables efficient access to an interleaved memory system that includes M modules, M being (2ⁿ+1) or (2ⁿ−1), n being a positive integer number. Upon receiving an address N, the controller performs shift and add/subtract operations to obtain a quotient of N divided by M based on a binomial series expansion of N over M. The controller computes a remainder of N divided by M based on the quotient. The controller then accesses one of the modules in the memory based on the remainder.

The invention belongs to the field of heapsort, and especially relates to a sorting method suitable for FPGA implementation. According to the sorting method suitable for FPGA implementation, through designing a new data structure, a binary tree structure of an existing heapsort algorithm is modified to be a 2k-ary tree, k>=2, the degree of parallelism of data comparison is increased, the number of layers of the tree is reduced, and therefore the number of times accessing the data is decreased. By utilization of the function of outputting multiple data in one clock of an RAM of an FPGA, 2k child nodes to be compared can be read out in one clock, and the data reading time is reduced. The 2k-ary tree structure is used, addresses of the child nodes are simply obtained by shifting and adding non-leaf node addresses, thereby facilitating data access in the implementation and reduction of complexity of the implementation. Sorting time delay can be largely reduced by the method, and real-time performance of a sorting module is improved.

A device for implementing a sum-of-products expression includes a first set of 2-input Shift-and-Add (2SAD) blocks receiving a coefficient set/complex sum-of-products expression for generating a first set of partially optimized expression terms by applying recursive optimization therein, a second set of 1-input Shift-and-Add (1SAD) blocks receiving response from the 2SAD blocks for generating a second set of partially optimized expression terms by applying vertical optimization therein, a third set of 2SAD blocks receiving recursively and vertically optimized response from the first set of 2SAD block and the second set of 1SAD blocks for generating a third set of partially optimized expression terms by applying horizontal optimization therein, a fourth set of 2SAD blocks receiving response from the blocks for generating a fourth set of partially optimized expression terms by applying decomposition and factorization, and a fifth set of 2SAD blocks receiving response from the fourth set of 2SAD blocks, for generating the final output.

The invention belongs to the application field of software radio and digital signal processing thereof, in particular to a low-complexity multiplier-free fixed-point FFT optimization method based on dynamic truncation. The method includes obtaining FFT input data bits N and input data; shifting the decimal fraction of each rotation factor by N bits to the left, and dividing the data into a real part and an imaginary part, wherein N is the number of bits of the input data; rounding up the real part and the imaginary part up and down respectively, so that they are approximated to integers; All integers are factorized to the second power, and the integer with the least number of additions is selected; The circuit is designed by using shift and addition, and the multiplication of the originalrotation factor is replaced by the shift and addition of the data itself. The present invention further reduces the number of adders while replacing conventional complex multipliers with shift and add-subtract. At the same time, the dynamic bit-truncation module is added to restrain the growth of data bits, reduce the consumption of hardware resources, improve the computing speed and improve the performance of the circuit.

A radiation image diagnosing system includes a tomosynthesis image capturing assembly for acquiring the data of a plurality of tomosynthetic sectional images. The acquired data of the tomosynthetic sectional images are processed to reconstruct a shift-and-add image by a shift-and-add processor. The acquired data of the tomosynthetic sectional images are also processed to reconstruct an FBP image by an FBP processor. The shift-and-add image and the FBP image are displayed parallel to each other on a display unit.

This invention describes a programmable, digital implementation to shift an arbitrary frequency, or various frequencies in various communication systems of the original signal in the frequency domain. The correspondent phase accumulation to perform the desired frequency shift per sampling instant is perfectly tracked by counting up or down a simple integer. Several arbitrary frequency shifters with different mathematical models are provided. The correspondent implementations with Look-Up-Tables (LUT) are derived for high-speed implementations without further calculations of the values of the sine and cosine functions every sampling instant. Furthermore, a simple shift-and-add phase rotation is described to replace the four required real multiplications. If the original complex signal contains only one-bit each from real part and imaginary part, a surprisingly simple implementation is derived and disclosed for the overall arbitrary frequency shift operation. Further simplifications are also disclosed to make this invention feasible for high sampling frequencies and small frequency drifts.

A multiplication engine is described in which a decision threshold engine utilizes a Y-adder powers of two shift table to iteratively generate shift-add combinations. The shift-add combinations are output in a sequence with decreasing levels of contribution wherein the accuracy of the associated multiplication increases up to any desired level of accuracy to meet the requirements of the application. The multiplication engine can be used for generating the combinations either statically or dynamically. One embodiment describes a Y-adder hardware slider table engine in which the shift table is implemented with shifters and adders that can be set for active state or pass through state, and selectively summed to generate a product result directly from the table without the need to combine shift and add hardware.

The invention provides an exponent arithmetic method and device; the method comprises the steps of storing a plurality of step values and corresponding calculation operating parameters; preprocessing input indexes according to the plus-minus of the input indexes; setting the initial value of add and shift data to be 1 when the exponent arithmetic is started; firstly comparing the processed indexes with the plurality of stored step values to select the step values of the indexes and corresponding exponent arithmetic parameters; carrying out substraction to the processed indexes and the selected step values and taking the result as the current indexes; comparing the current indexes with the plurality of stored step values to select the step values of the indexes and corresponding exponent arithmetic parameters again; in this way, comparing the current indexes with the stored step values without repetition until the current indexes are smaller than all the stored step values; carrying out shift operation or shift and add operation to the add and shift data according to the obtained exponent arithmetic parameters in each step; and finally processing the add and shift data according to the plus-minus of the input indexes and outputting the exponent arithmetic result.

The invention provides a testing device for a system, and the device is small in circuit scale and uses little electricity. The system combines multi-carrier, a MIMO scheme, and beam forming processing. For modulation signals of each carrier of an R layer quantity output by a layer frequency domain signal generation unit (31), a window function arithmetic operation unit (32) performs convolution arithmetic operation of frequency characteristics of a window function. On another aspect, for a beam forming equivalence arithmetic operation unit (52) performs an arithmetic operation process equivalent to the beam forming process with the input of propagation channel characteristics of each path which are output by a fading setting unit (51), and a Fourier transform unit (53) performs Fourier transform with the input of the arithmetic operation results. An arithmetic operation unit (54) performs multiplication on two operation results Ht and Fsym, obtains spectrum information of signals to be received in receiving antennas, and converts the obtained spectrum information into signals in the time domain through inverse Fourier transform processes performed by a time domain signal generation unit. A shift addition unit (34) shifts and adds the converted signals, to generate received signals of the receiving antennas.

A phased array sector scanning ultrasonic system includes a separate receive channel for each respective element in an ultrasonic transducer array. Each receive channel imparts a delay to the echo signal produced by each respective element. The delayed echo signals are summed to form a steered, dynamically focused and dynamically windowed receive beam even when the transmit beam does not emanate from the center of the array. The receiver has a beamformer including a multiplicity of beamformer channels. The beamformer dynamically increases delays to each channel without introducing unwanted discontinuities, by combining and synchronizing a FIFO and an interpolator. The interpolator uses "Wallace tree" adders to accumulate bit-shifted versions of the inputs. The number of additions is less than the number of bits which would be needed to represent equivalent coefficients. This reduces the hardware relative to a conventional implementation which incorporates multipliers with shifts and adds equaling the number of bits in the coefficients.