Sorting method suitable for FPGA implementation

A sorting method and a suitable technology, applied in the field of heap sorting, can solve the problems of large data volume sorting time consumption, unable to meet real-time requirements, etc., to achieve the effect of facilitating data access, reducing sorting time complexity, and reducing delay

Inactive Publication Date: 2017-11-28
UNIV OF ELECTRONICS SCI & TECH OF CHINA
View PDF0 Cites 10 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When implemented by FPGA, the existing algorithm is not conducive to the advantages of FPGA parallel computing, and the time cons

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Sorting method suitable for FPGA implementation
  • Sorting method suitable for FPGA implementation
  • Sorting method suitable for FPGA implementation

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0022] The present invention will be described below in conjunction with the accompanying drawings.

[0023] In this embodiment, the ISE integrated development tool and the modelsim simulation platform are used for running experiments. The simulation parameters are: the sequence length n=128, the element number of the tree is 32, namely k=5, and the data bit width is 16. Two dual-port RAMs with a depth of 128 are used to store the data to be sorted, which are used to read non-leaf nodes and child nodes of non-leaf nodes respectively, reducing data reading time. The write bit width of both RAM1 and RAM2 is 16, and the read bit width of RAM1 is 512. One clock can read 32 data, and all child nodes of non-leaf nodes can be read at one time. The output bit width of RAM2 is 16. Use For reading non-leaf nodes, the address of reading non-leaf nodes in RAM2 is the same as the address of child nodes of non-leaf nodes in RAM1. attached figure 1 is the structural block diagram of the s...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention belongs to the field of heapsort, and especially relates to a sorting method suitable for FPGA implementation. According to the sorting method suitable for FPGA implementation, through designing a new data structure, a binary tree structure of an existing heapsort algorithm is modified to be a 2k-ary tree, k>=2, the degree of parallelism of data comparison is increased, the number of layers of the tree is reduced, and therefore the number of times accessing the data is decreased. By utilization of the function of outputting multiple data in one clock of an RAM of an FPGA, 2k child nodes to be compared can be read out in one clock, and the data reading time is reduced. The 2k-ary tree structure is used, addresses of the child nodes are simply obtained by shifting and adding non-leaf node addresses, thereby facilitating data access in the implementation and reduction of complexity of the implementation. Sorting time delay can be largely reduced by the method, and real-time performance of a sorting module is improved.

Description

technical field [0001] The invention belongs to the field of heap sorting, in particular to a sorting method for FPGA realization. Background technique [0002] Sorting is a commonly used algorithm in engineering implementation. In the current software implementation, there are already many mature quick sorting algorithms, such as: selection sort, insertion sort, heap sort, etc. These sorts are designed for software and belong to serial implementation algorithms. The traditional algorithm cannot use the parallel operation of FPGA, which leads to a large time delay for FPGA to realize the sorting, which is not conducive to the realization of projects with high real-time requirements. [0003] Document 1 "Algorithm 232–Heapsort (by Williams, J.W.J.1964, Communications of the ACM 7(6):347–348.)" and Document 2 "Algorithm 245-Treesort 3 (by Floyd, Robert W.1964, Communications of the ACM 7 (12):701)" proposed the heap sorting algorithm and introduced the steps of heap sorting ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): G06F7/24
CPCG06F7/24
Inventor 袁东华王军刘宝城卢程程
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap