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85results about How to "Reduce read and write operations" patented technology

Address mapping method for flash translation layer of solid state drive

The invention discloses an address mapping method for a flash translation layer of a solid state drive. The method comprises the following steps of (1) establishing a cached mapping table, a cached split table, a cached translation table and a global translation directory in an SRAM (static random access memory) in advance; (2) receiving an IO (input/output) request, turning to a step (3) if the IO request is a write request, otherwise turning to a step (4); (3) preferentially and sequentially searching the tables in the SRAM for the hit condition of the current IO request, finishing write operation according to hit mapping information, and caching the mapping information according to a hit type and a threshold value; (4) preferentially searching the tables in the SRAM for the hit condition of the current IO request, and finishing read operation according to the hit mapping information in the SRAM. The method has the advantages that the random write performance of the solid state drive can be improved, the service life of the solid state drive can be prolonged, the efficiency of the flash translation layer is high, the hit ratio of address mapping information in the SRAM is high, and less additional read-write operation between the SRAM and the solid state drive Flash is realized.
Owner:NAT UNIV OF DEFENSE TECH

Method for interlacing rate matching and de-interlacing off-rate matching

The invention discloses an interlacing matching method. The method determines interlacing operators according to a column interlacing mode, and uses the sequence of the interlacing operators to carry out interlacing processing for a sub-block interlacing matrix, wherein in one mode, the method uses the interlacing operators to carry out the interlacing processing for bits needing to be output in the sub-block interlacing matrix according to the requirement of a redundancy version, and directly outputs sub-block interlacing results ordered by a protocol at the same time of finishing sub-block interlacing till reaching corresponding code rate requirement; and in the other mode, the method can use the interlacing operators to carry out the interlacing processing for the sub-block interlacing matrix one by one, outputs sub-block interlacing results ordered by the protocol to a cyclic buffer at the same time of finishing sub-block interlacing, and outputs corresponding interlaced bits according to the requirement of the redundancy version. Moreover, the invention also discloses a de-interlacing off-rate matching method corresponding to the interlacing rate matching method. The method can be applied to interlacing rate matching and de-interlacing off-rate matching, and greatly reduces used caches and read-write operations for the caches.
Owner:POTEVIO INFORMATION TECH CO LTD

Interleaving and rate matching and de-interleaving and rate de-matching methods

The invention discloses an interleaving and rate matching method. A correction interleaving mode is determined according to a column interleaving mode and head filling bits, an interleaving operator is determined according to the correction interleaving mode, and the interleaving operator is utilized to perform interleaving processing on subblock interleaving matrices in sequence; one mode can utilize the interleaving operator to perform the interleaving processing on bits required to be output in the subblock interleaving matrices according to the requirement of redundancy version, directly output subblock interleaving results after protocol sorting while completing the interleaving of subblocks until meeting the corresponding requirement of the code rate; and the other mode can utilize the interleaving operator to perform the interleaving processing on the subblock interleaving matrices one by one, output the subblock interleaving results after protocol sorting to a circulating buffer while completing the interleaving of subblocks, and then output corresponding bits after the interleaving according to the requirement of the redundancy version. Furthermore, the invention also discloses a de-interleaving and rate de-matching method corresponding to the interleaving and rate matching method. The methods can greatly reduce buffers to be used and read-write operation of the buffers in the interleaving and rate matching and de-interleaving and rate de-matching processes.
Owner:POTEVIO INFORMATION TECH

Method and system for achieving user port VLAN service management in ONU

ActiveCN103840996AEfficient implementation of configurationEfficient implementation of deletionNetworks interconnectionNetwork managementService configuration
The invention provides a method and system for achieving user port VLAN service management in an ONU. The method includes the steps that operation is carried out on related service hardware and logic according to VLAN service configuration data attribute tables, and the VLAN service configuration data attribute tables are saved in a first memory space of the ONU; a new table is formed according to VLAN service configuration data issued by a gateway and saved in a second memory space of the ONU; the related service hardware and logic and the VLAN service configuration data attribute tables in the first memory space are updated according to comparison results between table data in the first memory space and table data in the second memory space so as to bring service configuration into effect. By comparing new configuration and original configuration first according to the configuration data issued by network management software and then determining a next action according to marked content, user port VLAN service configuration and deletion can be efficiently achieved, VLAN service configuration states can be tracked comprehensively, specific requirements for hardware forms are avoided, and the method can be simplified and is short in implementation cycle.
Owner:FENGHUO COMM SCI & TECH CO LTD

Method and device for reading and processing raster data

The invention provides a method and device for reading and processing raster data, and relates to the technical field of space information services. The method comprises the following steps of separating a buffer into N buffer raster blocks in a server in advance, wherein the N buffer raster blocks are used for storing data of the N raster blocks; according toiming at the N buffer raster blocks, building a memory database, and generating a corresponding memory recording table, wherein the memory recording table is used for recording the use information of each buffer raster block; then, receiving a request for reading raster data from a client; and inquiring the memory recording table to judge whether the requested raster block data exist or not, wherein, if the requested raster block data exist, reading the raster block data are read from the buffer raster blocks and returneding the raster block data to the client, and if the requested raster block data do not exist, extracting the corresponding raster block data are extracted from a disc, and are storeding the corresponding raster block data into an empty buffer raster block or are alternatively selecteding to enter one buffer raster block, updating the records in the memory are updated, and returning the raster block data are returned to the client. The method and the device have the advantages that the processing efficiency of the raster data is improved, and the system resource is saved.
Owner:BEIJING DATUM TECH DEV

FPGA-based H.264 video encoding end, decoding end, transmission device and transmission method

The invention provides an FPGA-based H.264 video coding end, an H.264 video decoding end, a transmission device and a transmission method. The method comprises steps that H.264 video coding end videodata is sent; the H.264 video encoder receives the video data and starts encoding; each time 128-byte coded data is generated, the 128-byte coded data is sent to the AXI-MM-to-AXI-S module in real time, the AXI-MM-to-AXI-S module processes the coded data and then sends the coded data to the UDP Ethernet sending module, and the UDP Ethernet sending module starts sending every 128-byte data; after receiving the compressed code stream data packet, a UDP Ethernet receiving module of the H.264 video decoding end transmits the compressed code stream data packet to an RAM in an AXI-S-to-AXI-MM modulefor caching; after the AXI-S to AXI-MM module detects a data frame header, the AXI-S to AXI-MM module delays for 3ms and sends a decoding start interrupt to the decoding end main control module; andthe decoding end main control module controls the H.264 video decoder to start decoding, and the H.264 video decoder reads data from the RAM in the AXI-S-to-AXI-MM conversion module and decodes and outputs a video. The overall delay of a coding and decoding system is remarkably reduced, and the method is very suitable for low-bandwidth transmission modes such as wireless image transmission.
Owner:HUNAN JUNHAN INFORMATION TECH CO LTD
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