Method for interlacing rate matching and de-interlacing off-rate matching

Abstract

The invention discloses an interlacing matching method. The method determines interlacing operators according to a column interlacing mode, and uses the sequence of the interlacing operators to carry out interlacing processing for a sub-block interlacing matrix, wherein in one mode, the method uses the interlacing operators to carry out the interlacing processing for bits needing to be output in the sub-block interlacing matrix according to the requirement of a redundancy version, and directly outputs sub-block interlacing results ordered by a protocol at the same time of finishing sub-block interlacing till reaching corresponding code rate requirement; and in the other mode, the method can use the interlacing operators to carry out the interlacing processing for the sub-block interlacing matrix one by one, outputs sub-block interlacing results ordered by the protocol to a cyclic buffer at the same time of finishing sub-block interlacing, and outputs corresponding interlaced bits according to the requirement of the redundancy version. Moreover, the invention also discloses a de-interlacing off-rate matching method corresponding to the interlacing rate matching method. The method can be applied to interlacing rate matching and de-interlacing off-rate matching, and greatly reduces used caches and read-write operations for the caches.

Description

technical field [0001] The present invention relates to a rate matching technology, in particular to an interleaving rate matching and deinterleaving de-rate matching method. Background technique [0002] In a communication system, the function of rate matching is to adjust the code rate output by the channel encoder so that the number of bits output by the rate matching module matches the number of bits that can be carried by the physical resources allocated by the system. In the process of rate matching, it is generally combined with interleaving processing in order to realize a variable rate mechanism with superior performance and improve the stability of encoding performance at high code rates. [0003] Common interleaving methods can be divided into packet interleaving and convolutional interleaving. Packet interleaving, also known as matrix interleaving or block interleaving. In existing communication systems, such as 3GPP, 3GPP2 and other wireless communication tech...

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Problems solved by technology

[0008] From the above process, it can be found that figure 1 When the rate matching structure shown is implemented, there is the following problem: if the sub-block interleaver module, the bit collection module and the bit selection and pruning module are implemented as functional blocks, each module needs to use a buffer to temporarily store the intermediate results , and then the next module takes out the intermediate results from the buffer of the previous module for processing, which will introduce a large number of read and write operations on the buffer; although each sub-block can be processed in parallel when sub-block interleaving is performed, the same n sub-blocks The block interleaving process requires n identical hardware resources, and it is difficult to achieve resource sharing

if according to figure 1 The reverse process of the structure shown is implemented, and there are also disadvantages of many read and write operations on the buffer and difficult sharing of resources.

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