Address mapping method and system for FFT processor with completely parallel data

An address mapping and processor technology, applied in the field of FFT processors, can solve the problem of low data parallelism

Inactive Publication Date: 2004-06-16
宁波高新区中科芯元集成电路技术有限公司
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Problems solved by technology

Most of the early processors achieved high performance by improving the parallelism of operations, and the data parallelism was not high.

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  • Address mapping method and system for FFT processor with completely parallel data
  • Address mapping method and system for FFT processor with completely parallel data
  • Address mapping method and system for FFT processor with completely parallel data

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Embodiment Construction

[0017] FFT processor block diagram of the present invention sees figure 1 , it is mainly composed of the following parts: the butterfly operation unit can complete one radix 4 or two radix 2 operations per cycle; the operation data is stored in the dual-port memory according to certain rules, and the dual-port memory is divided into 4 storage Body (M0, M1, M2, M3), which can complete the parallel reading and writing of 4 input data and 4 output data each time; according to the requirements of the address mapping algorithm, a data exchange component is needed between the operation unit and the memory; the rotation Factors are stored in ROM, they are divided into three memory banks, and provide three rotation factors required by a radix-4 butterfly operation; the system control part is responsible for the control and synchronization of the internal data of the processor; the external data interface is responsible for communicating with the external communication of data.

[001...

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Abstract

The invention is a full-parallel FFT-processor address mapping method, storing operation number in dual-port memory and rotation factor in ROM; determining R / W addresses for operation number and rotation factor. It fully uses common address operation character of FFT algorithm itself, uses 4 data memory bodies and 3 rotation-factor ones, performs data input and output in the same location, is able to provide an operation number for a butterfly operation in each period and has maximum parallelity. During processor working, the rotation factor only demands simple one-increased mode addressing. It is applied to N point (N is the power of 2) FFT calculation, having high efficiency of base-4 operation and calculation range of base-2 operation.

Description

technical field [0001] The invention relates to an FFT processor, in particular to an address mapping method and system for radix-4 and mixed-radix (4+2) FFT processors. Background technique [0002] Discrete Fourier transform (DFT) is an important mathematical tool to describe the relationship between time domain and frequency domain of discrete signals. With the emergence of many fast calculation methods (FFT), it has been widely used in digital signal processing and image signal processing. It is the core operation of many systems. FFT has high requirements on operation speed and data access speed. To calculate an n-point base r FFT, you need (N / r)×log r N butterfly operations, and 2N×log r N data access operations. Most of the early processors achieved high performance by increasing the parallelism of operations, and the degree of data parallelism was not high. With the pipeline and parallel processing of computing components, compared with the data access speed, the...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/00G06F9/30G06F12/00
Inventor 谢应科
Owner 宁波高新区中科芯元集成电路技术有限公司
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