68 results about "Irreducible polynomial" patented technology

A condensed Galois field computing system including a multiplier circuit for multiplying first and second polynomials with coefficients over a Galois field to obtain their product; and a Galois field linear transformer circuit for applying an irreducible polynomial of power n to the product including a partial result generator responsive to terms of power n and greater in the product for providing a folded partial result and a Galois field adder for condensing the folded partial result and the terms less than power n in the product to obtain Galois field transformer of power n of the product.

A reduction operation is utilized in an arithmetic operation on two binary polynomials X(t) and Y(t) over GF(2), where an irreducible polynomial Mm(t)=t<m>+am-1t<m-1>+am-2t<m-2>+ . . . +a1t+a0, where the coefficients as are equal to either 1 or 0, and m is a field degree. The reduction operation includes partially reducing a result of the arithmetic operation on the two binary polynomials to produce a congruent polynomial of degree less than a chosen integer n, with m<=n. The partial reduction includes using a polynomial M'=(Mm(t)-t<m>)*t<n-m>, or a polynomial M''=Mm(t)*t<n-m >as part of reducing the result to the degree less than n and greater than or equal to m. The integer n can be the data path width of an arithmetic unit performing the arithmetic operation, a multiple of a digit size of a multiplier performing the arithmetic operation, a word size of a storage location, such as a register, or a maximum operand size of a functional unit in which the arithmetic operation is performed.

A Forward Error Correction (FEC) code compatible with the self-synchronized scrambler used by the 64B/66B encoding standard for transmission on Serializer/Deserializer (SerDes) communications channel links. The FEC code allows encoding and decoding to occur before and after scrambling, respectively, so as to preserve the properties of the scrambling operation on the transmitted signal. The code allows the correction of any single transmission error in spite of the multiplication by three of all transmission errors due to the 64B/66B scrambling process. A Hamming code is combined with a Bit Interleaved Parity code of degree n (BIP-n). These two codes provide for protection both for an error anywhere in the maximum length of the packet as well as for an error replicated two or three times by the descrambling process. All single bit errors, whether multiplied or not, have unique syndromes and are therefore easily correctable. In addition, the packet can be transported across multiple serial links for higher bandwidth applications without a degradation of the code efficiency. The Hamming code can be generated from any irreducible polynomial, such as H(x)=x¹⁰+x³+1. The BIP code is chosen to be of degree 6 to fit with 64B/66B scrambling polynomial and is represented by B(x)=x⁶+1.

An elliptic curve processing apparatus that performs operations on elliptic curves specified over binary polynomial fields includes a functional unit that has a digit serial multiplier with a digit size of at least two bits. The elliptic curve processing apparatus performs reduction for respective generic curves using arbitrary irreducible polynomials, which correspond to respective ones of the generic curves. The elliptic curve processing apparatus may include hardwired reduction circuits in the functional unit for use with respective named curves. A storage location in the elliptic curve processing apparatus may be used to specify whether an operation is for one of the named curves or for one of the generic curves. The elliptic curve processing apparatus responds to an arithmetic instruction to utilize a respective one of the hardwired reduction circuits for reduction for respective named curves and a multiplier circuit for reduction for a plurality of generic curves, the multiplier coupled to perform reduction for respective generic curves using arbitrary irreducible polynomials, the arbitrary irreducible polynomials corresponding to respective ones of the generic curves. The elliptic curve processing apparatus operable on elliptic curves specified over binary polynomial fields performs a conditional branch according to whether a curve being processed is a generic curve or a named curve.

A method whereby an encryption apparatus encrypts a message on the basis of a fibration X(x, y, t) serving as a public key when private keys are two or more sections corresponding to fibration X(x, y, t)=0 of an algebraic surface X, the method comprises embedding plaintext M obtained by concatenating the message to a random number as the coefficients of plaintext polynomial M(t) of degree l−1 or less, and generating encrypted text F=E_pk(M, p, q, f, X) from the plaintext polynomial M(t) by an encrypting process of performing operations including at least one of addition, subtraction, and multiplication of random polynomials p(x, y, t), q(x, y, t), a random irreducible polynomial f(t) of degree l or more, and the fibration X(x, y, t) with respect to the plaintext polynomial M(t).

An apparatus multiplies a first and a second binary polynomial X(t) and Y(t) over GF(2), where an irreducible polynomial Mm(t)=t<m>+am-1t<m-1>+am-2t<m-2>t<m-2>+ . . . +a1t+a0, and where the coefficients ai are equal to either 1 or 0, and m is a field degree. The degree of X(t)<n, and the degree of Y(t)<n, and m<=n. The apparatus includes a digit serial modular multiplier circuit coupled to supply a multiplication result of degree >=m of a multiplication of the first and second binary polynomials. The digit serial modular multiplier circuit includes a first and second register, each being <=n bits. A partial product generator circuit multiplies a portion of digit size d of contents of the first register and contents of the second register. The partial product generator is also utilized as part of a reduction operation for at least one generic curve.

An embodiment of the invention relates to a BCH encoder formed with linear feedback shift registers (LFSRs) to form quotients and products of input polynomials with irreducible polynomials of a generator polynomial g(x) of the BCH encoder, with and without pre-multiplication by a factor x^m. The BCH encoder includes multiplexers that couple LFSR inputs and outputs to other LFSRs depending on a data input or parity generation state. The BCH encoder can correct up to a selectable maximum number of errors in the input polynomials. The BCH encoder further includes LFSR output polynomial exponentiation processes to produce partial syndromes for the input data in a syndrome generation state. In the syndrome generation state the LFSRs perform polynomial division without pre-multiplication by the factor x^m. The exponentiation processes produce partial syndromes from the resulting remainder polynomials of the input data block.

A polynomial representation (b_i(x)) in an AES finite field

of input bytes (b_i) of a state matrix (B) is obtained. A plurality (1) of irreducible polynomials (f_i(y)) and a moving map (ψ_i) are used to map each polynomial (b_i(x)) of the polynomial representation into a respective field of polynomials

computed with respect to one of the irreducible polynomials (f_i(y)), to obtain respective moved polynomials (α_i(y)). The moved polynomials (α_i(y)) are mapped into a polynomial (a(z)) of a polynomial ring

obtained by applying an isomorphism (ω) between the fields of polynomials

and the polynomial ring

based upon the Chinese remainder theorem (CRT). AES encryption is applied to the polynomial (a(z)). The polynomial (a(z)) is reconverted into the AES finite field

to obtain an encrypted state matrix (CB).

A compact Galois field parallel multiplier engine includes a multiplier circuit for multiplying together two polynomials with coefficients over a Galois field to obtain their product; a Galois field linear transformer circuit has a multiply input from the multiplier circuit for predicting the modulo remainder of the polynomial product for an irreducible polynomial; first and second polynomial inputs; the Galois field linear transformer circuit may include a plurality of cells configured in a matrix section and a unity matrix section wherein the unity matrix section cells represent the prediction of the remainder when the output of the multiplier circuit is a polynomial with a power less than the power of the irreducible polynomial.

The invention discloses a finite field inversion method based on hardware design, which is applicable to an elliptical curve encrypt system. The method comprises the following steps: using a monadic polynomial in a finite field GF(p) as an input element a and defining an irreducible polynomial f(x), wherein a=am-1x+am-2x+to +a1x+a0, f(x)x=+fm-1xx+to +f(1)+f(0), ai and fi are respectively the coefficients of the input element a and the irreducible polynomial f(x); the input element a being repeatedly multiplied or divided by x and adding the results, and outputting the multiplicative inverse a of the input element a. Correspondingly, the invention further provides a finite field GF(2) inversion device based on the hardware design, therefore, the invention ensures rapider calculation speed, thereby greatly improving inversion operating efficiency. In addition, the working frequency of the inversion device is close to that of other operation devices in the encrypt system so as to fully improve the hardware source utilization rate of the inversion device.

A public key code hopping safety system and method mainly includes electronic unlocking key transmitting end and receiving end. It features transmitting end received touch-tone signal controlling program to execute ciphering transmit operation, reading out product serial number, encryption key, synchronous counter value, and irreducible polynomial Fm value from memory, then loading these data into ciphering unit, after complete ciphering and loading to shift register to transmit, after receiving end received signal, controlling procedure reading in serial number, deciphering encryption key, irreducible polynomial, synchronizing enumeration data from memory, to make deciphering and verifying, writing back new synchronizing count value to memory, in executing training pattern, writing back new serial number and deciphering encryption key to memory, when serial number is effective but deciphering invalidation, effectively deciphering outputting alarm signal, successfully learning, writing in new serial number, synchronous counter value, and deciphering encryption key for refreshing memory. Said invention has advantage of high system safety and low cost.

A Galois field divider engine and method inputs a 1 and a first Galois field element to a Galois field reciprocal generator to obtain an output, multiplies in a Galois field reciprocal generator a first Galois field element by a first element of the Galois field reciprocal generator for predicting the modulo remainder of the square of the polynomial product of an irreducible polynomial m−2 times where m is the degree of the Galois field to obtain the reciprocal of the first Galois field element, and multiplying in the Galois field reciprocal engine the reciprocal of the first Galois field element by a second Galois field element for predicting the modulo remainder of the polynomial product for an irreducible polynomial to obtain the quotient of the two Galois field elements in m cycles; in a broader sense the invention includes a compound Galois field engine for performing a succession of Galois field linear transforms on a succession of polynomial inputs to obtain an ultimate output where each input except the first is the output of the previous Galois field linear transform; Galois field square root is achieved by inputting a Galois field element to a Galois field square root generator to obtain an output which is squared in the Galois field square root generator to predict the modulo remainder of the square of the polynomial product of an irreducible polynomial m−1 times where m is the degree of the Galois field to obtain the square root of the Galois field to obtain the square root of the Galois field element in (m−1) cycles.

A method (500) of generating a cryptographic checksum for a message M(x) is provided. The method comprises pseudo-randomly selecting (502) at least two irreducible polynomials p i (x). Each irreducible polynomial p i (x) is selected based on a first cryptographic key from the set of irreducible polynomials of degree ni over a Galois Field. The method further comprises calculating (503) a generator polynomial p(x) of degree n = formula (I) as a product of the N irreducible polynomials formula (II), and calculating (505) the cryptographic checksum as a first function g of a division of a second function of M(x), (M(x)), modulo p(x), i.e., g( (M(x)) mod p(x)). By replacing a standard checksum, such as a Cyclic Redundancy Check (CRC), with a cryptographic checksum, an efficient message authentication is provided. The proposed cryptographic checksum may be used for providing integrity assurance on the message, i.e., for detecting random and intentional message changes, with a known level of security. Further, a corresponding computer program, a corresponding computer program product, and a checksum generator for generating a cryptographic checksum, are provided.

The invention provides a construction method of two-dimensional optical address codes suitable for visible light OCDMA (Optical Code Division Multiple Access) communication, and aims to solve the technical problems of limitation on wave number selection and difficulty in gaining both a large code set and a low cross-correlation value in the prior art. The method comprises the following implementation steps: generating a galois field according to an irreducible polynomial on a prime field; generating a mapping sequence according to a quadratic polynomial on the galois field; mapping a corresponding wavelength onto pulses of one-dimensional optical address codes according to the mapping sequence to obtain two-dimensional optical address codes; and grouping the two-dimensional optical address codes, and allocating a group of code words to each LEDs (Light Emitting Diodes) communication terminal in the visible light communication. In the construction method, the mapping sequence is generated through the quadratic polynomial on the galois field, so that selection of a two-dimensional optical address code wave number is more flexible. Moreover, the two-dimensional optical address codes are grouped, so that a visible light communication network can accommodate more users, and multi-user interference under the coverage of the same LEDs illuminating communication terminal is restrained.

The invention discloses a quantum digital signature and a quantum digital signcryption method. The quantum digital signature comprises the following steps: generating a secret key; generating a digital signature; and verifying the digital signature. The security of the hash function used in the signcryption or signature process is ensured by the irreducible polynomial and the hash function key serving as the input random number, and the irreducible polynomial depends on the local random number and cannot be known by a receiver and a signature verification party in advance before the signcryption or signature process; in other words, the unconditionally secure hash function is used so that the security of the whole signcryption or signature process is ensured, and the security risk caused by leakage of a fixed irreducible polynomial in other signatures is directly avoided; and moreover, the length of the message is not limited when the hash value is generated, the message with any length can be signed or signcrypted in each round of signature or signcryption, and the signature or signcryption efficiency is very high.

Galois-field reduction circuitry for reducing a Galois-field expansion value using an irreducible polynomial includes a plurality of memories, each for storing a respective value derived from the irreducible polynomial and a respective expansion bit position. Gates select ones of said the plurality of memories corresponding to ones of the respective expansion bit positions that contain ‘1’, and an exclusive-OR gate combines outputs of the gates that select. A specialized processing block includes a multiplier stage, and an input stage upstream of the multiplier stage, with such Galois-field reduction circuitry in the input stage with its output selectably connectable to the multiplier stage and selectably connectable to an output of the specialized processing block. A programmable integrated circuit device includes a plurality of such specialized processing blocks, and additional multiplier and additional exclusive OR gates for concatenating a plurality of specialized processing blocks.

The present invention relates to a finite field multiplier used for implementing an encrypting algorithm circuit, thereby minimizing power consumption and circuit area in implementing the finite field multiplier with a LFSR (Linear Feedback Shift Register) structure. The Finite field multiplier of the present invention is an operator performing a modular operation on the multiplication result of two data represented on a polynomial basis in a Galois Field into an irreducible polynomial. The LFSR structure is a serial finite field multiplication structure, and has a merit over an array structure and a hybrid structure in application to systems that are limited in size and power due to its simplicity of circuits and also its capability of being implemented in a small size.

A Galois field multiply/multiply-add/multiply-accumulate system (10) comprising a multiplier circuit for multiplying two polynomials with coefficients over a Galois field to obtain a product; a responsive multiplier circuit , a Galois field linear transformation circuit that predicts the modulo remainder of the polynomial product to an irreducible polynomial; used to provide a set of coefficients for the Galois field linear transformer circuit to predict the modulo remainder for a predetermined irreducible polynomial and a Galois field adder circuit that adds the product of the multiplier circuit to the third polynomial with coefficients in the Galois field to perform the multiplication and addition operations in a single cycle.

Techniques are provided for performing Galois field arithmetic to detect errors in digital data stored on disks. Two 12-bit numbers or two 10-bit numbers are multiplied together in Galois field using tower arithmetic. In the 12-bit embodiment, a base field GF(2) is first extended to GF(2³), GF(2³) is extended to a first quadratic extension GF(2⁶), and GF(2⁶) is extended to a second quadratic extension GF(2¹²). In the 10-bit embodiment, the base field GF(2) is first extended to GF(2⁵), and GF(2⁵) is extended to a quadratic extension GF(2¹⁰). Each of the extensions for the 10-bit and 12-bit embodiments is performed using an irreducible polynomial. All of the polynomials used to generate the first and the second quadratic extensions of the Galois field are in the form x²+x+K, where K is an element of the ground field whose absolute trace equals 1.

An apparatus for determining data signatures in a dynamic distributed device network may include a processor. The processor may be configured to receive a first query and generate a local partial closure of the data identified by the first query. The processor may be further configured to synthesize a data signature of the local partial closure. In this regard, the data signature may be an irreducible polynomial expression and the data signature may be orthogonal to remote data signatures generated from remote partial closures. Further, the processor may be configured to store the data signature in an information store within a dynamic distributed device network. Associated methods and computer program products may also be provided.

The invention relates to an all-in-one irreducible polynomial based finite field multiplier which comprises a controller, an input control module, an output control module, a finite field multiplier and an operation module, wherein the controller is used for controlling and scheduling data transmission among the input control module, the output control module and the finite field multiplier; the input control module is used for inputting a multiplication operation number a(x) and a multiplication operation number b(x) when detecting that a finite field GF(2n) has an all-in-one irreducible polynomial; the finite field multiplier is used for calling the operation module to carry out finite field multiplication operation on the multiplication operation number a(x) and the multiplication operation number b(x) to obtain a multiplication operation result c(x); the operation module is used for implementing and logical operation, exclusive or logic operation and modular operation; the output control module is used for outing the multiplication operation result c(x). By adopting the multiplier, the operation efficiency of finite field multiplication is improved.