14 results about "Irreducible polynomial" patented technology

The present invention discloses a method for constructing a Golomb Costas sequence based on a high-order spread domain, which belongs to the field of wireless communication technology. The method comprises the following steps: determining the order N of the Golomb Costas sequence to be constructed; and determining the order N of the Golomb Costas sequence to be constructed according to N=p. n ‑2, determine p, n, where p is a prime number and n is a positive integer, and explicitly state the extended field GF (p n ); select an irreducible polynomial of degree n with a leading coefficient of 1 on the prime field GF(p) as f(x), and clearly expand the field GF(p n ) in the form of elements, define the extended field GF(p n ) two binary operations on elements in the GF(p n ) primitive elements and their powers, and list the powers of primitive elements; in the extended field GF(p n ) selects two primitive elements; calculates the placement coordinates and completes the construction of the Golomb Costas sequence. The present invention calculates the primitive elements of the extended domain and their powers by calling functions such as get_combins(p,n), modBKY(p,n,BY,BKY,res) and calc(p,n,BKY,res_product), and according to the construction formula of the Golomb Costas sequence and by searching the extended domain GF(p n ) list of powers of primitive elements, quickly calculate the placement coordinates of the Golomb Costas sequence, reduce the workload of manual calculations, and improve the efficiency of constructing high-order Golomb Costas sequences based on extended domains. At the same time, it ensures the correctness of the calculation of the placement coordinates of the Golomb Costas sequence, solving the difficult problem of constructing Golomb Costas sequences based on high-order extended domains.

The application provides a decoding method, an encoding method, a device, a chip and a computing device. The method comprises the following steps: a decoding device acquires a first matrix, and then decodes a first code word vector according to the first matrix to obtain a decoding result. The first matrix is a 0-1 matrix representing elements in a second matrix on a polynomial ring. The second matrix is a check matrix on a finite field 2q, and the number of rows is r and the number of columns is n. A first polynomial corresponding to the polynomial ring is a q-th irreducible polynomial on a binary field. The number of 1s in the first matrix is less than the number of 1s in the 0-1 matrix representation of the second matrix. The first code word vector comprises k information code elements and r check code elements, and n=k+r. Each code element comprises q data units, and each data unit comprises at least one bit. The scheme can effectively reduce the hardware implementation complexity and cost of RS encoding and decoding.

The embodiment of the invention provides a data coding method, which comprises the following steps: acquiring a target matrix which is a check matrix or a generator matrix and is a binary matrix representing data units of a finite field 2a on a polynomial ring, the polynomial corresponding to the polynomial ring is an irreducible polynomial of which the highest number of times is not greater than a; according to the target matrix, encoding a data block to obtain an encoding result; wherein the coding result is used as a redundant data block of the data block; or the coding result is a recovery result of the data block of the node where the coding result is located. In the embodiment of the invention, one irreducible polynomial can be selected as the polynomial corresponding to the polynomial ring, so that the data unit of the finite field 2a can be converted to the corresponding polynomial ring to be expressed, and then the exclusive or operation equivalent to the multiplication operation can be carried out through the data expressed on the basis of the polynomial ring. And the calculation overhead is reduced.

The application discloses a processing method for a modulus exponent data generation task and related devices, wherein a classical computing unit constructs a quantum circuit for calculating a modulus exponent operation result of an input modulus and exponent in GF(2 k ) based on a preset irreducible polynomial, a base and a LUP decomposition method; and sends the exponent and the quantum circuit to a quantum computing unit; the quantum computing unit excites a quantum bit to an initial quantum state based on the exponent, drives the quantum bit to evolve from the initial quantum state based on the quantum circuit, obtains a measurement result of the quantum bit, and sends the measurement result to the classical computing unit; and the classical computing unit determines and outputs the modulus exponent operation result based on the measurement result; the quantum circuit is constructed by the irreducible polynomial, the base and the LUP decomposition method, and the exponent is taken as an input of the quantum circuit, so that the modulus exponent data in GF(2 k ) is efficiently generated, and classical encryption algorithms are accelerated to be cracked.

Provided in the present application are an encoding method and apparatus, and a decoding method and apparatus. The encoding method comprises: on the basis of a CRC polynomial, performing CRC encoding on A information bits to be encoded, so as to obtain a first bit sequence, wherein the first bit sequence comprises L CRC bits and A information bits; and performing polar encoding on the first bit sequence. Encoding that satisfies nesting property and irreducible polynomial requirements are realized on the basis of an improved CRC polynomial.

The application discloses an authentication encryption method, which shares random numbers and irreducible polynomial determination algorithms in a safe way, guarantees that both authentication parties share preset random irreducible polynomials, eliminates security loopholes caused by the cumulative failure probability of multiple rounds of authentication, and can replace the preset random irreducible polynomials by regularly replacing the random numbers in the later period; the absolute safe first key string and the second key string are shared in a safe way, the first key string and the preset irreducible polynomial are used to generate a LFSR hash matrix to generate a message authentication code, and the second key string is used for one-time one-encryption or decryption of the message, which theoretically provides the information theory security that can resist all existing attacks, and guarantees the confidentiality, integrity and authenticity of the information.

The present invention discloses a method for generating a dynamic S-box based on chaotic mapping and irreducible polynomials, which relates to the fields of chaotic cryptography and image encryption. The method specifically includes: S1: Serializing the plaintext; S2: Selecting a number of irreducible polynomials over the GF(2<supgt;^8< / supgt;) field, and using the iterative results of the Logistic chaotic mapping to select irreducible polynomials to participate in the calculation; Modifying the model formula of the Arnold mapping into a one-dimensional formula, optimizing the one-dimensional formula to obtain the S-box generation formula, and combining the selected irreducible polynomials with the S-box generation formula to generate the S-box; S3: Generating an extended key with the S-box; S4: Encrypting the plaintext sequence with the key; S5: Replacing the encrypted sequence with the S-box; S6: Changing the positions of the ciphertext sequence; S7: Iterating the operations of S2-S6 for 15 rounds. The dynamic S-box generated by the present invention can meet the requirements of the block encryption algorithm for the S-box, especially the performance requirements and time requirements of the image encryption algorithm for the S-box.

The invention discloses a configurable vectoring modular multiplier, comprising a plurality of modular multiplication units, each modular multiplication unit comprising: an input module for receiving a first input signal, a second input signal, a third input signal and a control signal; the first input signal is a first coefficient corresponding to the column number of the modular multiplication unit in the first polynomial; the second input signal is a second coefficient corresponding to the line number of the modular multiplication unit in a second polynomial; the third input signal is a third coefficient corresponding to the line number of the modular multiplication unit in the irreducible polynomial; the multiplication and addition module is used for performing vectorization multiplication and addition on an output vector, a second input signal and a first input signal according to bit block circulation, calling an update function to perform reduction operation on the output vector and a third input signal, and performing reduction operation on the output vector and the third input signal by the update function according to a control signal; and the output module is used for outputting the output vector outwards. According to the method, the dynamic MDS matrix vector multiplication can be efficiently supported without redundancy.

This application provides a data processing method and related apparatus. The method includes: generating a random irreducible polynomial corresponding to a target finite field using a target S-box in a target cryptographic algorithm; determining multiple linearly independent target elements using each element in the target finite field to form a random basis corresponding to the target finite field; generating a random S-box different from the target S-box using the random irreducible polynomial and the random basis; sending the random S-box to a data terminal for subsequent data processing of the data to be processed based on the target cryptographic algorithm, changing the target S-box to a random S-box, and obtaining the data processing result of the data to be processed. Compared with evolutionary algorithms, this method has lower computational complexity, reduces the consumption of computing resources, and lowers the computational load on the processor. Even in data processing scenarios based on target cryptographic algorithms with limited computing resources, it improves the security of data processing based on target cryptographic algorithms and ensures message security.

The present invention discloses a system for generating irreducible polynomials and hash algorithms based on an FPGA, relating to the field of information security. The system includes an irreducible polynomial unit and a hash algorithm unit. After detecting a flag data bit indicating the start of transmission, the system extracts irreducible polynomial parameters and inputs them into the irreducible polynomial unit. The irreducible polynomial unit then judges the irreducible polynomial parameters. Irreducible polynomial parameters that meet the requirements are input into the hash algorithm unit. The irreducible polynomial parameters, a key, and data to be encrypted are calculated by the hash algorithm unit to ultimately output a hash value. The system can not only quickly generate irreducible polynomials, but also quickly, securely, and efficiently implement hash algorithm encryption based on the irreducible polynomials.

Provided in the present application are a decoding method and apparatus, an encoding method and apparatus, and a chip and a computing device. The decoding method comprises: a decoding apparatus acquiring a first matrix, and then decoding a first codeword vector on the basis of the first matrix to obtain a decoding result, wherein the first matrix is a 0-1 matrix in which elements in a second matrix are represented on a polynomial ring, the second matrix is a check matrix having r rows and n columns on a finite field 2q, a first polynomial corresponding to the polynomial ring is an irreducible polynomial of a degree q on a binary field, and the number of "1"s in the first matrix is less than the number of "1"s in a 0-1 matrix representation of the second matrix; and the first codeword vector comprises k information symbols and r check symbols, where n=k+r, each symbol comprises q data units, and each data unit comprises at least one bit. The solution of the present application can effectively reduce the hardware implementation complexity and overheads of RS encoding and decoding.

Provided in the embodiments of the present application is a data encoding method, comprising: acquiring a target matrix, the target matrix being a check matrix or a generator matrix, the target matrix being a binary matrix which represents a data unit of a finite field 2a on a polynomial ring, and a polynomial corresponding to the polynomial ring being an irreducible polynomial of which the highest degree is not greater than the a; and encoding a data block according to the target matrix to obtain an encoding result, wherein the encoding result is used as a redundant data block of the data block, or the encoding result is a recovery result for a data block of a node where same is located. In the embodiments of the present application, an irreducible polynomial can be selected as a polynomial corresponding to the polynomial ring, such that the data unit of the finite field 2a can be converted to be represented on the corresponding polynomial ring, and then an XOR operation equivalent to a multiplication operation can be performed by means of data based on the polynomial ring representation, thus reducing computational overheads.

The application discloses a processing method of a modulo square data generation task and related devices, wherein a classical computing unit constructs a quantum circuit for calculating a modulo square operation result of input data in GF(2 k ) based on a preset irreducible polynomial and a LUP decomposition method, and sends the input data and the quantum circuit to a quantum computing unit; the quantum computing unit excites a quantum bit to an initial quantum state based on the input data, and drives the quantum bit to evolve from the initial quantum state based on the quantum circuit to obtain a measurement result of the quantum bit; the measurement result is sent to the classical computing unit; and the classical computing unit determines and outputs the modulo square operation result based on the measurement result, thereby realizing efficient generation of modulo square data in GF(2 k ), and further realizing acceleration of cracking of a classical encryption algorithm.

Provided in the embodiments of the present application is a data encoding method, comprising: acquiring a target matrix, the target matrix being a check matrix or a generator matrix, the target matrix being a binary matrix which represents a data unit of a finite field 2a on a polynomial ring, and a polynomial corresponding to the polynomial ring being an irreducible polynomial of which the highest degree is not greater than the a; and encoding a data block according to the target matrix to obtain an encoding result, wherein the encoding result is used as a redundant data block of the data block, or the encoding result is a recovery result for a data block of a node where same is located. In the embodiments of the present application, an irreducible polynomial can be selected as a polynomial corresponding to the polynomial ring, such that the data unit of the finite field 2a can be converted to be represented on the corresponding polynomial ring, and then an XOR operation equivalent to a multiplication operation can be performed by means of data based on the polynomial ring representation, thus reducing computational overheads.