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Galois field multiply/ multiply-add/multiply accumulate

A technique of multiplication and addition, applied in the field of Galois field multiplication/multiply-add/multiply-accumulate systems

Inactive Publication Date: 2005-04-20
ANALOG DEVICES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In smaller processors, however, one computational unit must perform all the functions, and each value requires two cycles to complete the multiplication and addition operations, so processing a set of n values ​​​​requires 2n cycles

Method used

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  • Galois field multiply/ multiply-add/multiply accumulate
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  • Galois field multiply/ multiply-add/multiply accumulate

Examples

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Embodiment Construction

[0024] In addition to the one or more preferred embodiments disclosed below, the invention is capable of other embodiments and of being applied or carried out in various ways. Accordingly, it should be understood that the present invention is not limited in application to the detailed construction and component arrangements set forth in the following description or illustrated in the accompanying drawings.

[0025] figure 1 Shown is a Galois field multiply / multiply-add / multiply-accumulate system 10 capable of selectively multiplying values ​​in register 14 and register 16 and providing their product to output register 11, or register 14 and the value in register 16 are multiplied and their product is summed with the value in register 15, and the result is provided to output register 11.

[0026] in the description figure 2 Before implementing embodiments of the present invention as follows, etc., the properties and operations of Galois field multiplication and addition are ...

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Abstract

A Galois field multiply / multiply-add / multiply-accumulate system includes a multiplier circuit for multiplying two polynomials with coefficients over a Galois field to obtain their product; a Galois field linear transformer circuit responsive to the multiplier circuit for predicting the modulo remainder of the polynomial product for an irreducible polynomial; a storage circuit for supplying to the Galois field linear transformer circuit a set of coefficient for predicting the modulo remainder for a predetermined irreducible polynomial; and a Galois field adder circuit for adding the product of the multiplier circuit with a third polynomial with coefficients over a Galois field for performing the multiplication and add operations in a single cycle.

Description

technical field [0001] The present invention relates to a Galois field multiply / multiply-add / multiply-accumulate system capable of performing multiply / multiply-add / multiply-accumulate operations in one cycle. [0002] related application [0003] This application claims priority to the following U.S. provisional applications: U.S. Provisional Application No. 60 / 334,662 (AD-239J), filed November 30, 2001, by Stein et al., entitled "GF2-ALU"; U.S. Provisional Application No. 60 / 341,635 (AD-299J), entitled "Galois Field Multiply-Add (MPA) Using GF2-ALU," filed Dec. 18, 2001; Stein et al. Dec. 18, 2001 U.S. Provisional Application No. 60 / 341,711 (AD-297J), entitled "Data Encryption Standard Method (DES) Using GF2-ALU and 8-Way Parallel Logical Unit Table," and Stein et al., Nov. 30, 2001 US Provisional Application No. 60 / 334,510 (AD-240J), entitled "Galois Field Multiplier System," filed on . Background technique [0004] Galois field multiplication, multiply-add and multiply...

Claims

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Application Information

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IPC IPC(8): G06F17/10G06F7/00G06F7/60G06F7/72H03M13/01
CPCG06F7/724
Inventor 约瑟夫·斯坦海姆·普里姆亚尼维·萨皮尔
Owner ANALOG DEVICES INC
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