50results about "Coding bounds" patented technology

The invention relates to the technical field of computers, and discloses an information source coding matrix data processing method based on a modified conjugate gradient algorithm. According to the method, sparsity constraint and a fixed-point quantization mechanism are fused in iterative optimization, and a sparse fixed-point coding matrix meeting hardware deployment requirements is directly generated through gradient shielding, correction conjugate parameter calculation and Armijo criterion line search and synchronous execution of hard threshold sparseness and fixed-point quantization after each update. According to the method, the sparsity constraint and the fixed-point quantization mechanism are embedded in the iteration process of the modified conjugate gradient algorithm, so that end-to-end alignment of coding matrix optimization and hardware deployment requirements is realized.

A shared decoder pool is susceptible to head-of-line blocking when the decoding of a given data block delays the decoding of other data blocks pipelined in the decoder. While the problem can be avoided by not using a pipeline operation, the benefits of pipelining would be lost. In one embodiment provided herein, the syndrome of an error pattern is calculated in parallel with data being written in an input buffer for the decoder. Parallelizing the syndrome calculation and the filling of the decoder's input buffer can avoid the head-of-line blocking problem noted above while still achieving the benefits of pipelining. In another embodiment, a similar technique is used in a bit error rate estimation scan (BES) operation. Other embodiments are provided.

The application relates to the field of signal processing and discloses a unified probability graph computing architecture power consumption optimization method, system, medium and equipment, which comprises the following steps: a unified probability graph for multiple tasks is used to perform sparse optimization on message passing data flow by dynamically regulating the message passing data flow in a probability iteration calculation process; and based on the optimized message passing data flow, the activation state of a memory-computing integrated array node is dynamically selected by a computing circuit of a memory-computing integrated characteristic device to improve the adaptability of the computing architecture and hardware resources. The application reduces the calculation-storage scale by deleting probability messages with low reasoning contribution and dynamically regulating the message passing data flow in the probability iteration calculation process, and the adaptability of the computing architecture and hardware resources is improved by dynamically selecting the activation state of the memory-computing integrated array node, so that the power consumption is further reduced.

This invention relates to the field of computer technology and discloses a method for processing source coding matrix data based on a modified conjugate gradient algorithm. This method integrates sparsity constraints and fixed-point quantization mechanisms in iterative optimization. Through gradient masking, modified conjugate parameter calculation, and Armijo criterion line search, and by synchronously performing hard-threshold sparsification and fixed-point quantization after each update, it directly generates a sparse fixed-point coding matrix that meets hardware deployment requirements. This invention achieves end-to-end alignment between coding matrix optimization and hardware deployment requirements by embedding sparsity constraints and fixed-point quantization mechanisms within the iterative process of the modified conjugate gradient algorithm.

A communication device may include: a processor configured to perform a procedure comprising: receiving a first consensus check code from a first communication device; receiving a second consensus check code from a second communication device; generating a combination code by network encoding the first consensus check code and the second consensus check code; and instructing the transmission of the combination code to the first communication device and to the second communication device.

When a state machine of the time sequence circuit is influenced by a single event upset (SEU) effect, a state code of the state machine is very easy to change, so that the state machine is in an invalid or error state and cannot be recovered, and the function of the time sequence circuit is failed. Aiming at a state machine based on Hamming distance-3 coding, the invention provides the low-overhead error detection circuit for the Hamming distance-3 five-bit state code, and the resource overhead in the error detection process is greatly reduced by simplifying the judgment logic of a detection unit.

A device includes a data path, a first interface connected to the data path and configured to receive a request from a processor package to write a data value to a memory address, and a controller connected to the data path and configured to receive the request to write the data value to the memory address and to calculate a Hamming code of the data value. The controller is configured to transmit the data value and the Hamming code on the data path. The device includes an external memory interleave connected to the data path. The external memory interleave is configured to receive the data value and calculate a test Hamming code of the data value and to determine whether to send the data value to an external memory interface to be written to the memory address based on a comparison of the Hamming code and the test Hamming code.

The application discloses a decoding reliability analysis method and device, an electronic device and a storage medium. The analysis method comprises the following steps: obtaining the number of bits of a decoding result, performing extension processing on a preset matrix array in a target encoding matrix based on the number of bits, determining a decoding output matrix based on the preset matrix array after the extension processing and an input decoding matrix, performing decoding decision on the decoding output matrix to obtain a decision output result, and analyzing the reliability of the decoding result based on the decision output result and decoding noise power. The application solves the technical problem that the decoding processing mode used in the related art is not accurate in judging the reliability of the decoding result.

The present application takes the position closed structure and the orthogonal component difference as the core, converts the information to be processed into the residual structure representation under the background reference state constraint, the background reference state is constructed by the receiving and transmitting parties according to the consistent generation rule, and can be used as the structural key or the key derivation reference in the safe scene, so that the transmission and storage load can be concentrated on the residual field and the necessary auxiliary field. The framework uniformly carries the encoding, compression, encryption, inversion, decoding and structured domain calculation and topological consistency reasoning, realizes the integration of compression and encryption, storage and calculation. The system improves the equivalent storage density and energy efficiency performance through structured aggregation, and provides consistent logical pointing and calculation basis for reconstruction and reasoning.

The invention discloses an analog circuit implementation method and device based on a unified probability graph computing architecture, equipment and a medium, and the method comprises the steps: building a unified signal model based on the common characteristics of a baseband signal processing task; representing the unified signal model as a unified probability graph model; obtaining an initialization probability of a variable node state value in the unified probability graph model; a storage and calculation integrated characteristic device is set, the storage and calculation integrated characteristic device comprises an initial input array, an iterative calculation array and a result output array, and node state values of the initial input array, the iterative calculation array and the result output array are configured based on the unified probability graph model; a driving vector is obtained based on the initialization probability to serve as input of the initial input array, the iterative calculation array is used for completing iterative calculation of mutual message passing of variable nodes and check nodes in the unified probability graph model, and when an iteration stop condition is met, the result output array outputs a processing result to complete a baseband signal processing task.

The present disclosure relates to a method for designing a base graph of a low-density parity-check code in a communication system, said base graph, and an encoding / decoding method and apparatus therefor. A communication device for performing encoding by using an LDPC code in a communication system, according to an embodiment of the present disclosure, may: identify a base graph to be used among a first base graph and a second base graph of the LDPC code, on the basis of the length and a code rate of information to be transmitted; and when the identified base graph is the second base graph, identify a plurality of index values constituting a parity check matrix on the basis of the second base graph. The plurality of index values are identified on the basis of row indices and column indices of a matrix corresponding to the second base graph, and lifting set indices for lifting of the base graph, and index values corresponding to at least one column index mapped to a specific row index among the row indices may be further used for the encoding.

Techniques for accessing memory by a memory controller, comprising receiving, by the memory controller, a memory management command to perform a memory management operation at a virtual memory address, translating the virtual memory address to a physical memory address, wherein the physical memory address comprises an address within a cache memory, and outputting an instruction to the cache memory based on the memory management command and the physical memory address.

The application belongs to the technical field of integrated circuits, and discloses a cracking method of an integrated circuit encryption circuit state machine, which comprises the following steps: 1, applying excitation to a netlist to extract information; 2, regarding the process of solving a key as a process of state machine reconstruction, and converting the problem into a constraint programming problem; 3, if the number of keys solved by the CP-SAT solver is 1, the attack is ended, and the unique correct key is obtained, otherwise, timing equivalence checking is performed by using Synopsys VC Formal SEQ Application, and further incorrect keys are excluded in combination with Oracles until the unique correct key or multiple equivalent keys are obtained. The attack duration of the application mainly depends on the size of the state machine and the inherent jump relationship in the state machine, and the attack time is short and the efficiency is high.

An estimation apparatus including a controller that reads information from a storage that stores a set of code and parameter used for communication and information indicating performance requested to achieve predetermined communication quality in communication using the code and parameter in association with each other, and estimates an SNR to be requested in an MLC (Multilevel Coding) using the code and parameter indicated by the inputted information.

The embodiment of the invention provides a binary linear code decoding method and device and a storage medium, and the method comprises the steps: receiving channel soft information, obtaining a check matrix, carrying out the hard decision of the channel soft information, obtaining a receiving sequence and a syndrome, and carrying out the decoding of a binary linear code if the value of the syndrome is not a zero vector. And sorting the receiving sequence and the check matrix according to the reliability of the channel soft information to obtain the sorted receiving sequence and check matrix. Performing XOR operation on column elements of the sorted check matrix corresponding to the test error mode generated according to the logic weight and the syndromes to obtain test error mode syndromes, and if the values of the test error mode syndromes are all not zero vectors, disturbing channel soft information by using disturbance noise, and if the values of the test error mode syndromes are not zero vectors, disturbing channel soft information; and repeatedly performing hard decision on the channel soft information to obtain a receiving sequence, a syndrome and a subsequent process. The decoding method provided by the invention is relatively low in overall decoding complexity, does not depend on the structure of a linear code, and has good universality.

A memory sub-system configured to: measure a plurality of sets of signal and noise characteristics of a group of memory cells in a memory device; determine a plurality of optimized read voltages of the group of memory cells from the plurality of sets of signal and noise characteristics respectively; generate features from the plurality of sets of signal and noise characteristics, including at least one compound feature generated from the plurality of sets of signal and noise characteristics; generate, using the features, a classification of a bit error rate of data retrievable from the group of memory cells; and control an operation to read the group of memory cells based on the classification.

The invention discloses an error correction code decoding method, a test system and a computer program product, and relates to the field of storage firmware error correction, the method is applied to a large-scale parallel processor, and the method comprises the following steps: receiving a coding bit of an error correction code to be decoded; the coding bits are obtained by carrying out coding modulation on original data used for simulation testing by the host end; distributing the coded bits to a plurality of stream processors, and using the plurality of stream processors to execute decoding operation on the coded bits in parallel; in any stream processor, a computing kernel is distributed for the processing stage of the decoding operation, and the computing kernel is used for executing the processing task of the corresponding processing stage in parallel. A multi-level task parallel processing mode of inter-stream parallel and intra-stream parallel is adopted, and a parallel architecture of a large-scale parallel processor is fully utilized for decoding, so that the decoding performance simulation time consumption of error correction codes is reduced, and the simulation efficiency is improved.

A signal processing method for simulating and adding noise to digital signals, wherein the method is characterized by comprising the following steps: Step 1: Collect the target digital signals or target digital signal traces to be subjected to noise addition processing; Step 2: Generating the white noise signals or white noise signal traces; Step 3: Perform a convolution operation on the target digital signals and the white noise signals to generate color-changing noise signals, or perform a convolution operation on the target digital signal tracks and the white noise signal tracks to generate color-changing noise signal tracks; Step 4: Add the generated color-changing noise signals to the target digital signals, or add the generated color-changing noise signal tracks to the target digital signal tracks.

Techniques for loading data, comprising receiving a memory management command to perform a memory management operation to load data into the cache memory before execution of an instruction that requests the data, formatting the memory management command into one or more instruction for a cache controller associated with the cache memory, and outputting an instruction to the cache controller to load the data into the cache memory based on the memory management command.

The invention relates to an LDPC error correction method and system based on adaptive adjustment, and belongs to the technical field of data processing.The method comprises the steps that performance indexes reflecting the error rate of current data are obtained, and the performance indexes at least comprise the bit error rate; the performance index is compared with a preset threshold value, a target code word scheme is selected from a plurality of pre-stored LDPC code word schemes according to a comparison result, and the plurality of LDPC code word schemes have different error correction capabilities; and switching the current LDPC codeword scheme into the target codeword scheme, and executing the target codeword scheme to perform error correction on the current data, thereby reducing the error rate of the current data. The LDPC error correction method and the LDPC error correction device have the effect of considering both the resource efficiency under the normal condition and the high-reliability LDPC error correction under the abnormal condition.

Systems, methods, and apparatus related to error correction in memory devices. In one approach, a memory device uses dedicated op-codes to generate, during programming operations, a pattern including known requested data errors. During reading operations on the memory device, the calibrated errors will be detected by the ECC engine of the memory device as read errors. This permits a host device to observe, in a controlled environment, how the ECC engine behaves and performs in a final manufactured memory product.

The invention discloses a multi-task-oriented computing architecture implementation method and device based on a unified probability graph, equipment and a medium, and the method comprises the steps: building a unified signal model based on the common characteristics of baseband signal processing tasks; representing the unified signal model as a unified probability graph model; setting message transmission between a variable node and a check node in the unified probability graph model, and determining an iterative operation unit; and processing the baseband signal processing task by multiplexing the iterative operation unit in a hardware circuit and a processor. In conclusion, the method can be widely applied to baseband signal processing.

The application discloses a simulation circuit implementation method and device based on a unified probability graph calculation architecture, equipment and a medium, comprising: establishing a unified signal model based on the common characteristics of baseband signal processing tasks; the unified signal model is characterized as a unified probability graph model; the initialization probability of the variable node state value in the unified probability graph model is obtained; a storage and calculation integrated characteristic device is set, the storage and calculation integrated characteristic device comprises an initial input array, an iterative calculation array and a result output array, wherein the node state values of the initial input array, the iterative calculation array and the result output array are configured based on the unified probability graph model; the driving vector is obtained as the input of the initial input array based on the initialization probability, the iterative calculation array is used to complete the iterative calculation of the mutual message transmission between the variable nodes and the check nodes in the unified probability graph model, when the iteration stopping condition is met, the result output array outputs the processing result, and the baseband signal processing task is completed.

The present method relates to a method by which a device receives a signal in a communication system, and an apparatus therefor, and to a method by which a reception device processes a signal in a communication system, and an apparatus therefor, the method comprising the steps of: receiving an encoded bit sequence; and decoding the encoded bit sequence in the direction from a root node to the lowest node on the basis of a binary tree structure, wherein, in the decoding step, decoding for a child node is skipped on the basis that a syndrome of a parent node satisfies a predetermined condition, and decoding for the child node is performed on the basis that the syndrome of the parent node does not satisfy the predetermined condition.

The invention relates to the field of signal processing, and discloses a unified probability graph calculation architecture power consumption optimization method and system, a medium and equipment, and the method comprises the steps: carrying out the sparse optimization of a message passing data flow through the dynamic regulation and control of the message passing data flow in a probability iterative calculation process for a multi-task unified probability graph; and based on the optimized message passing data stream, dynamically selecting a storage and calculation integrated array node activation state through a calculation circuit of a storage and calculation integrated characteristic device so as to improve the adaptation degree of a calculation framework and hardware resources. According to the method, a message transmission data stream in a probability iterative calculation process is dynamically regulated and controlled, and a probability message with low reasoning contribution is deleted so as to reduce a calculation-storage scale; and the activation state of the storage and calculation integrated array node is dynamically selected, the adaptation degree of the calculation architecture and hardware resources is improved, and the power consumption is further reduced.

To provide a quantum error correction method.SOLUTION: A quantum error correction method including correcting a stream of syndrome measurements produced by a quantum computer comprises receiving a layered representation of error propagation through quantum error detection circuits, where the layered representation comprises a plurality of line circuit layers that each represent a probability of local detection events in a quantum computer associated with one or more potential error processes in the execution of a quantum algorithm. During execution of the quantum algorithm, the method comprises: receiving one or more syndrome measurements from quantum error detection circuits; converting the syndrome measurements into detection events written to an array that represents a patch of quantum error correction circuits at a sequence of steps in the quantum algorithm; determining one or more errors in the execution of the quantum algorithm from the detection events according to the stored line circuit layers; and causing correction of the syndrome measurements based on the determined errors.SELECTED DRAWING: Figure 1

Provided is an estimation device comprising a control unit that: reads information from a storage unit in which are stored a set of parameters and symbols used in communication, and information indicating the performance required in order to realize a prescribed communication quality in communication in which the parameters and symbols are used, the set and the information being associated with one another; and estimates a SNR required in multilevel coding (MLC) in which the parameters and symbols indicated by inputted information are used.

Techniques for maintaining cache coherency comprising storing data blocks associated with a main process in a cache line of a main cache memory, storing a first local copy of the data blocks in a first local cache memory of a first processor, storing a second local copy of the set of data blocks in a second local cache memory of a second processor executing a first child process of the main process to generate first output data, writing the first output data to the first data block of the first local copy as a write through, writing the first output data to the first data block of the main cache memory as a part of the write through, transmitting an invalidate request to the second local cache memory, marking the second local copy of the set of data blocks as delayed, and transmitting an acknowledgment to the invalidate request.