26results about "Coding bounds" patented technology

The invention relates to the technical field of computers, and discloses an information source coding matrix data processing method based on a modified conjugate gradient algorithm. According to the method, sparsity constraint and a fixed-point quantization mechanism are fused in iterative optimization, and a sparse fixed-point coding matrix meeting hardware deployment requirements is directly generated through gradient shielding, correction conjugate parameter calculation and Armijo criterion line search and synchronous execution of hard threshold sparseness and fixed-point quantization after each update. According to the method, the sparsity constraint and the fixed-point quantization mechanism are embedded in the iteration process of the modified conjugate gradient algorithm, so that end-to-end alignment of coding matrix optimization and hardware deployment requirements is realized.

The application relates to the field of signal processing and discloses a unified probability graph computing architecture power consumption optimization method, system, medium and equipment, which comprises the following steps: a unified probability graph for multiple tasks is used to perform sparse optimization on message passing data flow by dynamically regulating the message passing data flow in a probability iteration calculation process; and based on the optimized message passing data flow, the activation state of a memory-computing integrated array node is dynamically selected by a computing circuit of a memory-computing integrated characteristic device to improve the adaptability of the computing architecture and hardware resources. The application reduces the calculation-storage scale by deleting probability messages with low reasoning contribution and dynamically regulating the message passing data flow in the probability iteration calculation process, and the adaptability of the computing architecture and hardware resources is improved by dynamically selecting the activation state of the memory-computing integrated array node, so that the power consumption is further reduced.

This invention relates to the field of computer technology and discloses a method for processing source coding matrix data based on a modified conjugate gradient algorithm. This method integrates sparsity constraints and fixed-point quantization mechanisms in iterative optimization. Through gradient masking, modified conjugate parameter calculation, and Armijo criterion line search, and by synchronously performing hard-threshold sparsification and fixed-point quantization after each update, it directly generates a sparse fixed-point coding matrix that meets hardware deployment requirements. This invention achieves end-to-end alignment between coding matrix optimization and hardware deployment requirements by embedding sparsity constraints and fixed-point quantization mechanisms within the iterative process of the modified conjugate gradient algorithm.

A communication device may include: a processor configured to perform a procedure comprising: receiving a first consensus check code from a first communication device; receiving a second consensus check code from a second communication device; generating a combination code by network encoding the first consensus check code and the second consensus check code; and instructing the transmission of the combination code to the first communication device and to the second communication device.

When a state machine of the time sequence circuit is influenced by a single event upset (SEU) effect, a state code of the state machine is very easy to change, so that the state machine is in an invalid or error state and cannot be recovered, and the function of the time sequence circuit is failed. Aiming at a state machine based on Hamming distance-3 coding, the invention provides the low-overhead error detection circuit for the Hamming distance-3 five-bit state code, and the resource overhead in the error detection process is greatly reduced by simplifying the judgment logic of a detection unit.

The present application takes the position closed structure and the orthogonal component difference as the core, converts the information to be processed into the residual structure representation under the background reference state constraint, the background reference state is constructed by the receiving and transmitting parties according to the consistent generation rule, and can be used as the structural key or the key derivation reference in the safe scene, so that the transmission and storage load can be concentrated on the residual field and the necessary auxiliary field. The framework uniformly carries the encoding, compression, encryption, inversion, decoding and structured domain calculation and topological consistency reasoning, realizes the integration of compression and encryption, storage and calculation. The system improves the equivalent storage density and energy efficiency performance through structured aggregation, and provides consistent logical pointing and calculation basis for reconstruction and reasoning.

An estimation apparatus including a controller that reads information from a storage that stores a set of code and parameter used for communication and information indicating performance requested to achieve predetermined communication quality in communication using the code and parameter in association with each other, and estimates an SNR to be requested in an MLC (Multilevel Coding) using the code and parameter indicated by the inputted information.

A memory sub-system configured to: measure a plurality of sets of signal and noise characteristics of a group of memory cells in a memory device; determine a plurality of optimized read voltages of the group of memory cells from the plurality of sets of signal and noise characteristics respectively; generate features from the plurality of sets of signal and noise characteristics, including at least one compound feature generated from the plurality of sets of signal and noise characteristics; generate, using the features, a classification of a bit error rate of data retrievable from the group of memory cells; and control an operation to read the group of memory cells based on the classification.

The invention discloses an error correction code decoding method, a test system and a computer program product, and relates to the field of storage firmware error correction, the method is applied to a large-scale parallel processor, and the method comprises the following steps: receiving a coding bit of an error correction code to be decoded; the coding bits are obtained by carrying out coding modulation on original data used for simulation testing by the host end; distributing the coded bits to a plurality of stream processors, and using the plurality of stream processors to execute decoding operation on the coded bits in parallel; in any stream processor, a computing kernel is distributed for the processing stage of the decoding operation, and the computing kernel is used for executing the processing task of the corresponding processing stage in parallel. A multi-level task parallel processing mode of inter-stream parallel and intra-stream parallel is adopted, and a parallel architecture of a large-scale parallel processor is fully utilized for decoding, so that the decoding performance simulation time consumption of error correction codes is reduced, and the simulation efficiency is improved.

A signal processing method for simulating and adding noise to digital signals, wherein the method is characterized by comprising the following steps: Step 1: Collect the target digital signals or target digital signal traces to be subjected to noise addition processing; Step 2: Generating the white noise signals or white noise signal traces; Step 3: Perform a convolution operation on the target digital signals and the white noise signals to generate color-changing noise signals, or perform a convolution operation on the target digital signal tracks and the white noise signal tracks to generate color-changing noise signal tracks; Step 4: Add the generated color-changing noise signals to the target digital signals, or add the generated color-changing noise signal tracks to the target digital signal tracks.

The invention relates to an LDPC error correction method and system based on adaptive adjustment, and belongs to the technical field of data processing.The method comprises the steps that performance indexes reflecting the error rate of current data are obtained, and the performance indexes at least comprise the bit error rate; the performance index is compared with a preset threshold value, a target code word scheme is selected from a plurality of pre-stored LDPC code word schemes according to a comparison result, and the plurality of LDPC code word schemes have different error correction capabilities; and switching the current LDPC codeword scheme into the target codeword scheme, and executing the target codeword scheme to perform error correction on the current data, thereby reducing the error rate of the current data. The LDPC error correction method and the LDPC error correction device have the effect of considering both the resource efficiency under the normal condition and the high-reliability LDPC error correction under the abnormal condition.

The application discloses a simulation circuit implementation method and device based on a unified probability graph calculation architecture, equipment and a medium, comprising: establishing a unified signal model based on the common characteristics of baseband signal processing tasks; the unified signal model is characterized as a unified probability graph model; the initialization probability of the variable node state value in the unified probability graph model is obtained; a storage and calculation integrated characteristic device is set, the storage and calculation integrated characteristic device comprises an initial input array, an iterative calculation array and a result output array, wherein the node state values of the initial input array, the iterative calculation array and the result output array are configured based on the unified probability graph model; the driving vector is obtained as the input of the initial input array based on the initialization probability, the iterative calculation array is used to complete the iterative calculation of the mutual message transmission between the variable nodes and the check nodes in the unified probability graph model, when the iteration stopping condition is met, the result output array outputs the processing result, and the baseband signal processing task is completed.

The present method relates to a method by which a device receives a signal in a communication system, and an apparatus therefor, and to a method by which a reception device processes a signal in a communication system, and an apparatus therefor, the method comprising the steps of: receiving an encoded bit sequence; and decoding the encoded bit sequence in the direction from a root node to the lowest node on the basis of a binary tree structure, wherein, in the decoding step, decoding for a child node is skipped on the basis that a syndrome of a parent node satisfies a predetermined condition, and decoding for the child node is performed on the basis that the syndrome of the parent node does not satisfy the predetermined condition.

Provided is an estimation device comprising a control unit that: reads information from a storage unit in which are stored a set of parameters and symbols used in communication, and information indicating the performance required in order to realize a prescribed communication quality in communication in which the parameters and symbols are used, the set and the information being associated with one another; and estimates a SNR required in multilevel coding (MLC) in which the parameters and symbols indicated by inputted information are used.

This application provides a low-density parity-check (LDPC) decoding method, electronic device, and storage medium, relating to the field of communication technology. The method includes: obtaining the processor model of a user terminal and matching the system computing power information corresponding to the processor model; obtaining the decoding time of a first test case corresponding to a LDPC decoding test case; obtaining the maximum number of iterations based on the system computing power information and the first test case decoding time; and performing LDPC decoding based on the maximum number of iterations when data to be decoded is received. In this application, the maximum number of iterations is determined collaboratively by combining system computing power information and test case decoding time, allowing LDPC decoding to be performed using this maximum number of iterations. This satisfies the communication performance requirements of the communication system while reducing the bit error rate of LDPC decoding to a certain extent, thereby reducing the number of data retransmissions.

The application discloses a circuit implementation method and device based on a unified probability graph calculation architecture, equipment and a medium, comprising: establishing a unified signal model based on the common characteristics of baseband signal processing tasks; expressing the unified signal model as a unified probability graph model; expressing the message passing from check nodes to variable nodes in the unified probability graph model as a unified signal processor architecture; pre-storing a node state matrix into a memory-computing integrated device to obtain a memory-computing operator array, driving a vector as an input analog quantity of the memory-computing operator array, and a state value probability vector as an analog quantity output by the memory-computing operator array; updating the analog quantity output by the memory-computing operator array to obtain the message passing from variable nodes to check nodes in the unified probability graph model, and inputting the same as the input of the memory-computing operator array again to enter iteration; completing iterative calculation based on a set iteration condition, and realizing a baseband signal processing task.

Systems, methods, and apparatus related to error correction in memory devices. In one approach, a memory device uses dedicated op-codes to generate, during programming operations, a pattern including known requested data errors. During reading operations on the memory device, the calibrated errors will be detected by the ECC engine of the memory device as read errors. This permits a host device to observe, in a controlled environment, how the ECC engine behaves and performs in a final manufactured memory product.

The invention discloses a meteoric trail channel-oriented PAC code construction and interleaving method, which comprises the following steps of: obtaining an interleaving pattern by adopting an enumeration mode, interleaving an under-secret meteoric trail physical channel W through the interleaving pattern to obtain a new LLR sequence under the physical channel W, obtaining an above LLR mean value through iterative calculation, calculating an error probability according to a Q function and the above LLR mean value, and constructing a PAC code according to the error probability. And obtaining an information bit set through the error probability, obtaining a block error rate after interleaving according to the error probability and the information bit set, and selecting an interleaving pattern causing the lowest block error rate as a final interleaving pattern by comparing the block error rates of N interleaving patterns. According to the method, the error code performance of the PAC code is improved, and the reliability of a stream residue system can be greatly improved.

This invention belongs to the field of communication signal processing technology, specifically relating to a bit-by-bit iterative decoding device for Polar codes based on probability calculation. It aims to solve the problems of high decoding latency, large hardware overhead, area redundancy, and high power consumption in existing random computation-based Polar code BP decoders. The scheme consists of three main modules: a random number engine, a bit stream generation module, and iterative decoding. The random number engine generates uniform, low-correlation random numbers, which are shuffled to supply data for subsequent modules. The bit stream generation module achieves efficient conversion from LLR to random bit stream through noise-dependent scaling and direct comparison methods. The iterative decoding module adopts a sparse topology architecture with discrete-interval random injection, combined with a ping-pong operation register group between adjacent stages to achieve fully parallel pipeline iteration. It also differentiates the deployment of GCU update modules for odd and even stages and introduces a frozen bit optimization technique to shut down invalid operation units. This invention significantly reduces decoding latency, reduces hardware area and dynamic power consumption, retains the low-cost advantage of random computation, improves decoding efficiency and hardware utilization, adapts to the low-latency requirements of modern communication, and has strong engineering application value.

The invention discloses a power and degree distribution joint optimization method and system suitable for two-user LDPC codes under unequal powers, and the method comprises the following steps: 1, analyzing the constraint relation between the nodes of the two-user LDPC codes, and on the premise of successful decoding of the two users, taking the maximization of the total rate as the target, and carrying out the optimization of the degree distribution of the two-user LDPC codes; deriving a mutual information transfer objective function of LDPC codes of two users under unequal power; 2, solving the mutual information transfer target function in the step 1 according to a fixed point theory to obtain a check node degree analytical expression; and step 3, according to the check node degree analytic expression obtained in the step 2, dividing a degree distribution value area capable of enabling the LDPC codes of the two users to be successfully decoded in a power and degree distribution joint parameter space, screening out the optimal degree distribution, and solving the maximum total rate of the two users. According to the method, the problem of performance limitation caused by neglecting the coupling relationship between power and degree distribution in a power asymmetric scene in the prior art is solved, and the maximization of the total rate of the system is realized.

The disclosure relates to a method for identification via channels in a system having a plurality of data processing devices. The method comprises selecting, in a first data processing device, an identifier indicative of a target second data processing device of a plurality of second data processing devices; determining, in the first data processing device, an outer codeword from the identifier using an outer code comprising a first outer code and a second outer code; determining, in the first data processing device, an optical orthogonal codeword from the outer codeword using an optical orthogonal code; determining, in the first data processing device; a randomly selected codeword from the optical orthogonal codeword using an error correction code; and emitting the selected codeword from the first data processing device via a channel. Further, a computer program product and a system for identification via channels are provided.

The application relates to the field of signal processing and discloses a data flow optimization method, system, medium and equipment for adapting uniform probability graph calculation and a hardware circuit, acquires a probability graph model, realizes mutual message transmission between variable nodes and check nodes in the probability graph model based on a hardware circuit; wherein the probability graph model comprises variable nodes, check nodes and undirected edges, the undirected edges are used for connecting the variable nodes and the check nodes which have a connection relationship; message transmission is iteratively updated to realize data flow rescheduling, an iterative multiplication unit is determined in the transmitted message, and the iterative multiplication unit is subjected to data flow optimization to reduce the power consumption of the hardware circuit. The application can reduce the calculation complexity and support low-power hardware implementation of the probability graph calculation.

A data processing method and apparatus, relating to the field of communication technology. In this method, a first communication device adjusts the distributed matcher code rate to a second distributed matcher code rate R. DM2 Furthermore, based on the code rate R of the second distribution matcher DM2 The information bit sequence is processed by distribution matching to obtain a second bit sequence. This second bit sequence is then encoded using a low-density parity-check code to obtain a third bit sequence. Finally, the third bit sequence is modulated to obtain a first symbol sequence. This embodiment of the application, which adjusts the distribution matcher code rate to minimize the number of shortened bits in the sequence to be encoded, ensures the integrity of the base map, thus improving encoding / decoding performance and consequently enhancing communication performance.

A quantum element (QE) at a network node stores a first quantum state constituent (QSC) of an entangled quantum state characterized by a non-factorable quantum relationship among QSCs comprising the first QSC and a second QSC stored at another QE at another network node. Managing one or more quantum error management (QEM) operations includes: (1) providing a schedule for the QEM operations that is based at least in part on at least a portion of a time over which the first QSC is stored at the first QE and an estimated fidelity of the entangled quantum state after at least one of the QEM operations, or (2) providing a type of one or more QEM operations selected from two or more different types based at least in part on a number of resource quantum elements available at the first node after the first QSC is stored at the first QE.

The application discloses a multi-task computing architecture implementation method and device based on a unified probability graph, equipment and a medium, comprising: establishing a unified signal model based on the common characteristics of baseband signal processing tasks; the unified signal model is represented as a unified probability graph model; message passing between variable nodes and check nodes in the unified probability graph model is set to determine an iterative operation unit; and the baseband signal processing task is processed by multiplexing the iterative operation unit in a hardware circuit and a processor. In summary, the application can be widely applied in baseband signal processing.

Power consumption of read / write operations of a processor is reduced by encoding data values. An input value of a plurality of input values with a uniformly distributed random probability is mapped to one of a predefined set of codes, wherein the input value is mapped to a code that comprises more bits than the input value. The codes corresponding to the input value are outputted, wherein compared to an input value having a relatively low value, an input value having a relatively high value is mapped to a code of the pre-defined set of codes which either: (i) is closer to a target Hamming Weight, or (ii) has closer to a target number of bit flips within the code.