77 results about "Processor model" patented technology

A system for classifying a driver's driving skill of a vehicle based on behavioral diagnosis. A plurality of vehicle sensors providing vehicle measurement signals. A maneuver qualification and identification processor qualifies and identifies characteristic maneuver identifying signals and a maneuver index and parameter processor creates a maneuver index and identifies relevant vehicle parameters. A path reconstruction processor reproduces an intended vehicle path for each characteristic maneuver identified by the maneuver characteristic processor. A maneuver model processor models the characteristic maneuvers and a driving skill diagnosis processor provides driving skill signals based on the maneuver model and driver input data. The driving skill diagnosis processor converts the maneuver model signals and the driver command input signal to the frequency domain to provide frequency content discrepancy analysis.

Core model processing of a processor model PE1 and a processor model PE2 is serialized. Therefore, processing time for the inter-core-model communication is required between the core model processing of a first processor model and the core model processing of a second processor model. The inter-core-model communication processing is performed such that the inter-core-model communication required for the simulation processing of a multi-processor model is performed in parallel with the core model processing.

The present invention belongs to the field of automatic computer verifying technology, and is the CPU restraint creating and verifying method based on boundary condition and random self test. The specific mode is one random test environment including system structure model and RTL model. The system structure model is expected processor model realized with C simulator and used as the standard reference model. The RTL model is one to be tested and verified, and the random test and verification aims at testing the consistency of the RTL model to the system structure model. Both the RTL model and the system structure model can output separate processor state in each clock period, and comparing the processor state of these two model can judge the consistency. The present invention has independent system structure, and can constitute new verifying platform easily to raise the verification speed and quality greatly.

The present disclosure relates to a system and method for capturing log messages in a post-processing debugging environment. Embodiments may include receiving a processor model associated with an electronic design and generating, using one or more processors and the processor model, a complete view of the state of the memory. Embodiments may further include writing, using one or more processors and the processor model, a log message whenever a designated message logging function is reached within the complete view of the state of the memory.

The invention relates to an instruction optimization processor for RSA encryption algorithm. The instruction optimization processor for RSA encryption algorithm adopts five extension instructions specially used for accelerating optimization on RSA encryption algorithm, and designs a special instruction processor model-RSA_ASIP corresponding to a new instruction set. The five extension instructions specially used for accelerating optimization on RSA encryption algorithm include getbit, shift_l, shift_r, muladd and muladd2 instructions, and the special instruction processor model-RSA_ASIP corresponding to the new instruction set consists substantially of a data memory, a code memory, a register file, a pipeline and a bus matrix. According to the RSA_ASIP processor designed by the invention, the execution of the RSA can be greatly optimized on the premise of ensuring flexibility and extensibility of software realization; through realization on RSA1024 and RSA2048, the instruction period is shortened by 64 percent on average compared with the realization on an ARM (Advanced RISC (Reduced Instruction-Set Computer) machines) processor, and the processor model after being subjected to instruction optimization can save resource consumption.

Disclosed are a method and a device for realizing compatibility of different processors. The method includes the steps of obtaining configuration information and processor model of a single board under a single board standby state, updating the parameters related to the processor in the configuration information according to the processor, if the processor model information in theconfiguration information is different from the processor model, and modifying configuration of a flash memory sheet, so that the processor is connected with the flash memory where the BIOS program of the process is stored.

An input motion acquiring unit acquires a motion trajectory of an object from an image recognizing unit. A dynamic modeling processor models a plurality of robot motion patterns stored in a robot motion pattern storage unit in a dynamic system form, and stores the modeled robot motion patterns into a robot-motion-pattern-model storage unit. A motion converting unit linearly transforms the plurality of robot motion dynamic models stored in the robot-motion-pattern-model storage unit into prediction motion trajectories. A motion comparing unit compares the input motion trajectory acquired by the motion acquiring unit with the prediction motion trajectories transformed by the motion converting unit. A robot motion selecting unit selects a robot motion pattern having the highest similarity from the robot motion pattern storage unit. The present invention is applicable to a robot apparatus.

The invention provides a method for multiple broadcasting and repeating on the Intel IXP2400 network processor, which belongs to computer network communication field, the method includes: the receiving model receives the message from the outer port, which is transmitted to the enclosing model (EM) after being processed by the processor model, the enclosing model (EM) searches the multi-broadcast adjoined enclosing table (DMAT) according to the index of multiple broadcast (MID), the table is a chain table, each item stores a export message enclosing format information, then sends a multi-broadcast message head buffer, the message head content is stored in the buffer, forms the multi-broadcast message head META, the META is looped at front of the message SOP META, forms a message chain table, the message is transmitted to the queue managing model (QM), the transmitting dispatching model (TXS) dispatches the package to the transmitting model (TX), then the message is transmitted by the transmitting model. The invention amends the message head only, the body is not duplicated, and the repeating efficiency is high.

The invention provides a remote combined unattended medical infusion monitoring system, which comprises an infusion monitoring module, a wireless communication module, an information display module and a power supply module, wherein the infusion monitoring module comprises a main control module, a gravity sensor module, an infrared sensor module and an alarm module which are connected with the main control module; the central processor model of the main control module is MSP430F149REV; the gravity sensor module is mounted on a hook of an infusion frame; an infrared pipe sensor, which is U-shaped, is mounted on the outer wall above a Murphy dropper; the alarm module consists of a buzzer, a triode and a resistor; the wireless communication module is connected with the main control module andcarries out wireless transmission of information through a ZigBee technology; the wireless communication module comprises a chip with a model number of CC2530; and the information display module is connected with the wireless communication module. The situation that monitoring and alarming cannot be realized due to failure of a single sensor is solved, and the combined signal monitoring is reliable and has high accuracy.

A method and apparatus estimate hydrogen concentration in a reformate stream produced by a fuel processor of a fuel cell. A sensor measures carbon monoxide, carbon dioxide, and water in the reformate stream. A fuel meter controls fuel input to the fuel processor. An air meter controls air input to the fuel processor. A water meter controls water input to the fuel processor. A transport delay estimator recursively estimates transport delay of the fuel processor. A hydrogen estimator associated with the transport delay estimator, the air, water and fuel meters, and the sensor estimates hydrogen concentration in the reformate stream. The hydrogen estimator includes a fuel processor model that is adjusted using the estimated transport delay. The carbon monoxide, the carbon dioxide and the water are measured using a nondispersive infrared (NDIR) sensor.

The invention discloses a register renaming method and a system for an out-of-order high-performance processor. The method comprises the steps of constructing a parameterized processor model of an electronic system level ESL based on a high-level language, converting processor core components into an actual circuit through a hardware generator, and the core components comprise an instruction information classifier and a register renaming component for optimizing the structure of a reordering buffer; analyzing actual processor performance in real time and determining related parameters of the core component through a performance monitoring component composed of one or more hardware counters; and the performance monitoring component is used for counting performance data of the branch predictor component, the instruction information classifier, the reordering buffer, the renaming buffer and the instruction distribution component of the processor. In addition, based on the optimized register renaming structure, a fine-granularity instruction in-advance retirement mechanism is realized, and the performance of the processor can be further improved.

A telecommunications network capacity planning system. The telecommunications network capacity planning system includes a telecommunications network including a telecommunications services provider, subscribers and a network coupling the telecommunications services provider and the subscribers for provisioning of the telecommunications services. A database system is used for collecting and storing data at the user-level associated with provisioning of telecommunication services over the telecommunications network. A processor is coupled to the database system. The processor models the telecommunications network by generating upward projections from the stored user-level data and transforms the modeling of the network to a visual display of capacity information and network parameters for manipulation to evaluate capacity planning scenarios.

The invention discloses a design verification method of a special instruction processor. The method comprises the following steps: optimizing a target algorithm; dividing the target algorithm into a plurality of basic instruction blocks; converting the basic instruction blocks into a data flow diagram, and searching optimizable instruction blocks from the basic instruction blocks according to a preset instruction design rule by adopting a method of approximate optimal solution; designing special instructions of the searched optimizable instruction blocks and extending an original instruction set; and establishing a special instruction processor model and carrying out simulation verification on the special instruction processor model. According to the design verification method of the special instruction processor, the operating speed of the target algorithm for executing the modules with relatively high complexity in the realization process is improved through an instruction set extension method, so that the execution efficiency of the algorithm is improved.

Computing device, computer instructions and method for denoising marine seismic data recorded with first and second seismic sensors. The method includes receiving first seismic data recorded with the first sensor in a time-space domain; receiving second seismic data recorded with the second sensor in the time-space domain, wherein the first and second seismic data are recorded at the same locations underwater; calculating with a processor models of the first and second seismic data in a transform domain that is different from the time-space domain; performing a wavefield separation using the first and second datasets in the transform domain; determining a noise in the transform domain corresponding to the second seismic data based on the wavefield separation; reverse transforming the noise from the transform domain into the time-space domain; and denoising the second seismic data by subtracting the noise in the time-space domain from the second seismic data.

The invention discloses a hybrid heterogeneous virtualization communication method and a chip, and belongs to the technical field of embedded chips on chips. The method comprises the following steps:allocating a virtual network card to each operating system existing in a chip, and setting a corresponding IP address, so that an application program can achieve cross-operating-system interconnectionand intercommunication in a unified manner (socket) through a routing process of virtual and real gateways. Due to the fact that the application programs can be interconnected and intercommunicated between the physical cores and can also be interconnected and intercommunicated between the physical cores and the virtual machine, the chip is changed into an on-chip distributed system based on network communication logically from an original heterogeneous multi-core processor model. In addition, the method disclosed by the invention can be conveniently expanded to a system-on-chip with more physical cores and virtual machines.

A processor or CPU architecture that implements many enabling technologies proven to enhance data through put supporting the synchronous burst data transfer. The Input-Output (I/O) is uniformly viewed and treated as an individual First-In-First-Out (FIFO) device. Pluralities of memory areas are implemented for user stack, kernel stack, interrupt stack and procedure call stack. Only one I/O arbiter is necessary for a CPU model that arbitrates between a plurality of FIFOs substituting data caches for on-chip implementation, thus eliminating traditional data transfer techniques using Direct-Memory-Access (DMA), bus control and lock signals leaving just the interrupt signals and the new synchronous signals for an easy and streamlined system design and CPU model. Supporting an interrupt-driven, FIFO-based I/O and synchronous burst data transfer the CPU employs a simple linear large register sets without bank switching.

In an approach to modelling population movement scenarios, one or more computer processors receive at least one credential of a user. The one or more computer processors determine, based, at least in part, on the received at least one credential, at least one context of a first population movement scenario, wherein the at least one context provides scenario-specific information for the first population movement scenario. The one or more computer processors receive a plurality of parameters associated with the first population movement scenario. The one or more computer processors model, based, at least in part, on the determined at least one context and the received plurality of parameters, the first population movement scenario. The one or more computer processors generate at least one visualization of the first population movement scenario model.

The invention relates to an instruction optimization method for an Sbox generation process in an AES (Advanced Encryption Standard) encryption algorithm and a design of an instruction set processor model thereof. In order to accelerate the Sbox generation process in the AES algorithm, the invention designs three new extended instructions: (1) ifand(src1),(src2),(xor_src1),(xor_src2), for accelerating in-domain multiplication operation in the Sbox generation process; (2) getbit(dest)=(src),(bitpos), for accelerating bit-getting operation in the affine transformation process; and (3) xor5(dest)=(src1),(src2),(src3),(src4),(src5), for accelerating quinary exclusive-or operation in the affine transformation process. The three instructions are completed within one clock cycle; but in the traditional ARM (Advanced RISC Machines) processor, the three instructions respectively need multiple clock cycles. Thus, the new instructions achieve the accelerating effect. The invention also designs a special instruction processor model (SASIP) corresponding to the new instruction set according to the new extended instructions. The processor model realizes the extended instructions on hardware logic, thereby being a processor model specializing in AES-Sbox acceleration.

A method to verify an implemented coherency algorithm of a multi processor environment on a single processor model is described, comprising the steps of:

• • generating a reference model reflecting a private cache hierarchy of a single processor within a multi processor environment,
  • stimulating the private cache hierarchy with simulated requests and/or cross invalidations from a core side and/or from a nest side,
  • augmenting all data available in the private cache hierarchy with two construction dates and two expiration dates, set based on interface events,
  • wherein multi processor coherency is not observed if the cache hierarchy ever returns data to the processor with an expiration date that is older than the latest construction date of all data used before.

Further a single processor model and a computer program product to execute said method are described.