11 results about "Processor model" patented technology

The embodiment of the application discloses a kind of collaborative evaluation method for exploring the upper limit of processor micro-architecture performance and related device, the method includes that various idealized micro-architecture components are constructed according to the collaborative process of ideal model by real processor model, processor micro-architecture performance is collaboratively evaluated, and collaborative process includes: real processor model sends instruction query and information request to ideal model, and the request carries the memory address of dynamic instruction;Ideal model executes dynamic instruction according to memory address and obtains target value in normal working state, and target value is returned as the response of the request to real processor model;Real processor model executes dynamic instruction and obtains actual value in execution phase;Target value and actual value are verified in submission phase, and verification result is obtained.Using the embodiment of the application, the theoretical performance upper limit of value prediction and other speculative execution techniques can be accurately quantified, and the real performance bottleneck of the entire processor system integrated with the technique can be identified.

This application discloses an FC network simulation method, apparatus, and electronic device based on a simulation platform, relating to the field of optical communication network simulation technology. The method includes: configuring simulation parameters and constructing an FC node model to generate FC packets. An FC switch model is constructed based on the simulation parameters, including a switch port model, a message distribution model, and a switch processor model. The switch port model includes cascaded ports, achieving accurate simulation of large-scale networks. FC packets are sent from the FC node model to the switch port model and then uploaded to the message distribution model via the switch port model. Based on the message distribution model, the FC packets are distributed to the switch processor model or cascaded ports according to packet field information. Based on the switch processor model or cascaded ports, the FC packets are cached and forwarded to the corresponding target node model based on priority, achieving a reliable distribution mechanism and improving the adaptability of the simulation.

A multi-processor model hybrid simulation system and method are disclosed. The system includes: a hybrid model integration module for integrating multiple processor simulation models of different precision and applications, and providing a standardized unified interface conforming to a specific interface standard to the outside world through a dedicated adapter; multiple general-purpose peripheral modules, each designed according to the specific interface standard, for providing simulated peripheral capabilities when the processor simulation models are operating; and a parameterized control module for controlling the operation of one of the multiple processor simulation models according to user-configured operating mode parameters. This system fundamentally solves the problem of repetitive modeling caused by incompatibility of interfaces and modeling methods between simulation models of different technology stacks (such as QEMU and Verilator), and enables a single SoC general-purpose peripheral model to be seamlessly reused when processor simulation models of different precision and applications are operating.

The embodiment of the application provides a message processor function verification method and device, electronic equipment and a storage medium, and relates to the chip test technical field.The above method comprises the following steps: selecting an instruction matched with an instruction type defined by a target verification template from a special instruction library of a message processor to be verified, the special instruction library recording an instruction type and a parameter format of a special instruction of the message processor, the instruction type being an instruction type associated with a message processing flow; filling parameters for the selected instruction based on the parameter format of the selected instruction, so as to obtain a function verification instruction sequence; inputting a test message into a message processor model in a simulation environment, and driving the message processor model by using the function verification instruction sequence, so as to obtain a processing result output by the message processor model; and performing function verification on the message processor based on the processing result. By applying the scheme provided in the embodiment of the application, the function verification efficiency of the message processor can be improved.

A routing data management method, apparatus and device, and a computer readable storage medium, the method comprising: calculating a storage address of routing data based on a processor model, the storage address being determined by a multi-objective optimization algorithm to separate the routing data from application software; and based on a routing template and routing data, generating a data file containing the storage address and a routing data line, so that a supplier end reads the storage address in the data file, writes the routing data into a specified area in a processor according to offset, and dynamically loads the routing data through address mapping, the data file is used for transmitting the routing data, the technical problem that the development cost and the management difficulty are increased due to the fact that the routing data is lack of effective management in related technologies is solved, unified management and control of the routing data by a main engine plant are achieved, the development workload of the main engine plant is reduced, and meanwhile the supplier adaptation cost is reduced.

The application relates to the technical field of software data processing, in particular to a method and system for upgrading home appliance control software. The method comprises the following steps: collecting the processor model, storage capacity, communication interface type and sensor state of the device to form hardware configuration information before starting the software upgrade process of the home appliance; judging whether the device hardware meets the running requirements of the preset new version software based on the hardware configuration information; if not, suspending the upgrade process and prompting the user with hardware incompatibility information; if yes, evaluating the storage space memory resources of the home appliance according to the hardware configuration information. The application realizes the efficiency of the home appliance control software upgrade through the memory resource optimization allocation technology, dynamic communication adjustment technology and data integrity recovery technology, thereby improving the overall stability of the home appliance upgrade process.

The invention relates to the technical field of chip verification, and provides a to-be-tested design verification method, device, equipment and medium, and the method comprises the steps: determining a target execution function from at least two execution functions in a verification environment based on management logic and arbitration logic in a C language direct programming interface (DPI)-C processor model; based on the target execution function, calling a homonymy function execution program corresponding to the target execution function from a program library; and verifying the to-be-tested design based on the homonymous function execution program. According to the method, the DPI-C processor model is used for replacing a real processor, the execution program is directly called according to the management logic and the arbitration logic of the DPI-C processor model, verification of the to-be-tested design is achieved, the situation that according to the specification of the execution program of the processor, the simulation speed is increased, and the iteration verification efficiency is improved is avoided.

The invention relates to the technical field of computers, and discloses a real-time task scheduling method and system oriented to embedded heterogeneous multi-core parallel computer.The method achieves reasonable distribution and real-time completion of parallel tasks through cooperation of a processor model, a task model and a task scheduling algorithm. And the resource utilization rate of the heterogeneous multi-core processor and the task execution flexibility are improved. Real-time task scheduling can be realized for more than three types of processors or accelerators on a built board-level integrated unified addressing shared memory processing architecture, and optimization targets comprise performance parameters of task completion time, operation energy consumption, resource utilization rate and task switching times. Meanwhile, the dynamic scheduling flexibility is achieved, different allocation strategies are used for different types of tasks by utilizing local queues and key tasks, and meanwhile, the tasks can be dynamically migrated according to the running states of the tasks and the performance condition of the system, so that load balancing of computing resources is achieved.

The utility model belongs to the technical field of circuit boards of artificial intelligence equipment, in particular to a 100pin AI core board, which is characterized in that a plurality of pins are arranged on a side plate of a PCB (printed circuit board) of the 100pin AI core board, data interfaces formed by the pins comprise a microphone interface, a loudspeaker interface, a UART (universal asynchronous receiver / transmitter) interface and a GPIO (general purpose input / output) interface, the model of a processor on the PCB is RV1106G3, and the model of the processor on the PCB is RV1106G3. The processor has remarkable advantages in the aspects of computing power, image processing, coding, audio processing, low power consumption and the like, can meet operation and intelligent processing requirements when being used in the fields of security and protection equipment, image acquisition equipment, face recognition equipment and the like by being matched with different data interfaces, has good video data acquisition and processing functions, and can be widely applied to the fields of security and protection equipment, image acquisition equipment, face recognition equipment and the like. And various framework network models can be efficiently converted, and the requirements of intelligent equipment on data processing, image optimization and multi-camera cooperative work can be met.

The embodiment of the invention discloses a collaborative evaluation method for processor micro-architecture performance upper limit exploration and a related device, and the method comprises the steps: constructing various ideal micro-architecture components according to a collaborative process of a real processor model and an ideal model, and cooperatively evaluating the performance of a processor micro-architecture, the collaboration process comprises the following steps: the real processor model sends an instruction query and information request to the ideal model, wherein the request carries a memory address of a dynamic instruction; the ideal model executes the dynamic instruction according to the memory address in a normal working state to obtain a target value, and the target value serves as a response of the request and is returned to the real processor model; the real processor model executes the dynamic instruction in the execution stage to obtain an actual value; and verifying the target value and the actual value in the submission stage to obtain a verification result. By adopting the embodiment of the invention, the theoretical performance upper limit of a speculation execution technology such as value prediction can be accurately quantized, and the real performance bottleneck of the whole processor system integrated with the technology can be identified.

A system for automatically generating auto-scaling configurations for graphics processing unit (GPU) models is described. A provides users a platform to perform a load and performance (LnP) test on a model of a GPU of a computing device. The LnP test may result in a set of metrics associated with the GPU model. For example, the metrics may include throughput metrics (e.g., transactions per second (TPS)) and GPU utilization metrics. In some examples, the metrics may be based on a service level agreement (SLA), which may include latency, error rate, and GPU utilization requirements. Based on a scaling threshold determined from the metrics and a utilization requirement, the system may output an auto-scaling configuration for the GPU model. The GPU may operate using the auto-scaling configuration, where the auto-scaling configuration may enable the GPU model to scale up or scale down, for example, based on changes in traffic.