27 results about "Processor model" patented technology

The invention discloses a multi-dimensional collaborative AI training processor benchmark evaluation device and method. According to end-to-end performance evaluation, TTA and throughput indexes are obtained through a standardized training process; the operator support degree evaluation adopts a dynamic parameter generation technology to evaluate the speed-up ratio and the floating point performance utilization rate of calculation-intensive and memory-access-intensive operators; the energy consumption evaluation calculates a power consumption delay product based on steady-state power consumption monitoring. And finally, integrating multi-dimensional indexes through an analytic hierarchy process model and a fuzzy theory, realizing level mapping by adopting a four-section membership function, and finishing multi-level aggregation evaluation in combination with matrix operation. According to the method, three dimensions of performance, operator support degree and energy efficiency are creatively integrated, the problems of single evaluation index and high environment dependence of the heterogeneous AI processor are solved through automatic container deployment, dynamic parameter generation and steady-state power consumption monitoring technologies, and a comprehensive and quantifiable evaluation basis is provided for processor model selection.

The invention provides a cross-database SQL (structured query language) dynamic conversion adaptation method based on a responsibility chain, which comprises the following steps of: loading adaptation processors into the responsibility chain, and sequencing the processors to finish system initialization operation; according to the configuration file parameters, whether SQL adaptive conversion configuration is started or not is judged, and if yes, whether SQL conversion cache is started or not continues to be judged; when the SQL conversion cache is started, SQL conversion is executed, cache query is carried out, and available SQL statements of a target database are output. According to the method, one-time development and multi-database adaptation are achieved, the migration maintenance cost is greatly reduced, the opening and closing principle is achieved through a plug-in type, a responsibility chain and a multi-processor mode, future expansion, enhancement or customization are facilitated, and concurrency efficiency and adaptation flexibility are guaranteed.

The invention discloses a communication performance test method and device and a storage medium, and relates to the technical field of communication, and the method comprises the steps: after network configuration is completed, according to a topological relation of a peripheral component interconnection standard device corresponding to a host machine, obtaining a communication performance test result; and constructing a test link comprising the server-side second-type processor, the server-side network port, the client-side second-type processor and the client-side network port, and executing a stand-alone graphics processor remote direct memory access test on the test link. By the adoption of the technical scheme, testing can be completed on a single machine, a server and a client do not need to be arranged on different computing nodes, computing resources are saved, meanwhile, a testing link does not need to be manually configured, unified configuration of processor models, network card drivers and the like of the different computing nodes is not needed, and configuration requirements are reduced.

The invention provides a decoding method of a low-density parity check code, electronic equipment and a storage medium, and relates to the technical field of communication. The method comprises the following steps: acquiring a processor model of a user terminal, and matching system computing power information corresponding to the processor model; obtaining a first case decoding time corresponding to a low density parity check (LDPC) decoding test case; and obtaining the maximum number of iterations according to the system computing power information and the first case decoding time, and performing LDPC decoding based on the maximum number of iterations when the to-be-decoded data is received. According to the LDPC decoding method and device, the maximum number of iterations is cooperatively determined in combination with the two aspects of system computing power information and use case decoding time, LDPC decoding is carried out through the maximum number of iterations, the requirement of a communication system for communication performance is met, the error rate of LDPC decoding is reduced to a certain extent, and therefore the number of retransmission times of data is reduced.

Disclosed is an apparatus for predicting a 3D structure of a patient-tailored implant, including a memory that stores at least one instruction for predicting the 3D structure of the patient-tailored implant, and a processor that executes an operation according to the instruction, wherein the processor models a correlation between a 2D meniscus shape and a 3D meniscus shape, and predicts the 3D meniscus shape based on 3D shape features derived from modeling results.

The invention relates to the technical field of software data processing, in particular to an upgrading method and system for household appliance control software. The method comprises the following steps: before the household appliance starts a software upgrading process, acquiring a processor model, a storage capacity, a communication interface type and a sensor state of the appliance to form hardware configuration information; based on the hardware configuration information, judging whether the equipment hardware meets preset operation requirements of new-version software, if not, pausing an upgrading process, and prompting a user of hardware incompatibility information; and if yes, evaluating the memory resources of the storage space of the household appliance according to the hardware configuration information. According to the invention, through the memory resource optimization distribution technology, the dynamic communication adjustment technology and the data integrity recovery technology, the high efficiency of the household appliance control software upgrading is realized, so that the overall stability of the household appliance upgrading process is improved.

The embodiment of the application discloses a kind of collaborative evaluation method for exploring the upper limit of processor micro-architecture performance and related device, the method includes that various idealized micro-architecture components are constructed according to the collaborative process of ideal model by real processor model, processor micro-architecture performance is collaboratively evaluated, and collaborative process includes: real processor model sends instruction query and information request to ideal model, and the request carries the memory address of dynamic instruction;Ideal model executes dynamic instruction according to memory address and obtains target value in normal working state, and target value is returned as the response of the request to real processor model;Real processor model executes dynamic instruction and obtains actual value in execution phase;Target value and actual value are verified in submission phase, and verification result is obtained.Using the embodiment of the application, the theoretical performance upper limit of value prediction and other speculative execution techniques can be accurately quantified, and the real performance bottleneck of the entire processor system integrated with the technique can be identified.

The invention discloses an FC network simulation method and device based on a simulation platform and electronic equipment, and relates to the technical field of optical communication network simulation, and the method comprises the steps: configuring simulation parameters, constructing an FC node model, and generating an FC message. And an FC switch model is constructed based on the simulation parameters, the FC switch model comprises a switch port model, a message distribution model and a switch processor model, the switch port model comprises cascade ports, and accurate simulation of a large-scale network is realized. Sending the FC message to a switch port model through the FC node model, and uploading the FC message to a message distribution model through the switch port model; based on a message distribution model, distributing the FC message to a switch processor model or a cascade port according to the message domain information; according to the method, the FC message is cached based on the switch processor model or the cascade port, and is forwarded to the corresponding target node model based on the priority, so that a reliable distribution mechanism is realized, and the simulation adaptability is improved.

This application discloses an FC network simulation method, apparatus, and electronic device based on a simulation platform, relating to the field of optical communication network simulation technology. The method includes: configuring simulation parameters and constructing an FC node model to generate FC packets. An FC switch model is constructed based on the simulation parameters, including a switch port model, a message distribution model, and a switch processor model. The switch port model includes cascaded ports, achieving accurate simulation of large-scale networks. FC packets are sent from the FC node model to the switch port model and then uploaded to the message distribution model via the switch port model. Based on the message distribution model, the FC packets are distributed to the switch processor model or cascaded ports according to packet field information. Based on the switch processor model or cascaded ports, the FC packets are cached and forwarded to the corresponding target node model based on priority, achieving a reliable distribution mechanism and improving the adaptability of the simulation.

The invention discloses an automatic testing method of equipment, electronic equipment and a storage medium, and relates to the technical field of computers, a target central processing unit model and a target graphics processing unit model are obtained, and a test case for a voltage regulation module is determined in a sample library according to the target central processing unit model and the target graphics processing unit model; corresponding test schemes can be automatically obtained for central processing units and graphic processing units of different models, and the problems that in a traditional manual test mode, repeated work is large, efficiency is low, and errors are prone to occurring are solved. Through the scheme of automatically determining the test case and executing the automatic test, the test efficiency and accuracy of the voltage regulation module are remarkably improved, the technical problem of errors caused by manual operation is solved, the performance of the firmware of the voltage regulation module is optimized based on the firmware optimization scheme of the voltage regulation module, and the test efficiency of the voltage regulation module is improved. The technical effect that the voltage regulation module can better adapt to the power management requirements of central processing units and graphic processing units of different models is achieved.

A multi-processor model hybrid simulation system and method are disclosed. The system includes: a hybrid model integration module for integrating multiple processor simulation models of different precision and applications, and providing a standardized unified interface conforming to a specific interface standard to the outside world through a dedicated adapter; multiple general-purpose peripheral modules, each designed according to the specific interface standard, for providing simulated peripheral capabilities when the processor simulation models are operating; and a parameterized control module for controlling the operation of one of the multiple processor simulation models according to user-configured operating mode parameters. This system fundamentally solves the problem of repetitive modeling caused by incompatibility of interfaces and modeling methods between simulation models of different technology stacks (such as QEMU and Verilator), and enables a single SoC general-purpose peripheral model to be seamlessly reused when processor simulation models of different precision and applications are operating.

The embodiment of the application provides a message processor function verification method and device, electronic equipment and a storage medium, and relates to the chip test technical field.The above method comprises the following steps: selecting an instruction matched with an instruction type defined by a target verification template from a special instruction library of a message processor to be verified, the special instruction library recording an instruction type and a parameter format of a special instruction of the message processor, the instruction type being an instruction type associated with a message processing flow; filling parameters for the selected instruction based on the parameter format of the selected instruction, so as to obtain a function verification instruction sequence; inputting a test message into a message processor model in a simulation environment, and driving the message processor model by using the function verification instruction sequence, so as to obtain a processing result output by the message processor model; and performing function verification on the message processor based on the processing result. By applying the scheme provided in the embodiment of the application, the function verification efficiency of the message processor can be improved.

The invention discloses a method for loading peripheral settings of a processor and a server system, and relates to the technical field of servers, the method comprises the following steps: reading a base address of a bidirectional two-wire system serial bus, writing memory read-write capability enabling and transmission configuration enabling into a preset offset address space of a corresponding base address, and then, loading the peripheral settings of the processor into a preset offset address space of the corresponding base address; and reading data of a specific address from the memory by using a multi-byte reading mode of a bidirectional two-wire system serial bus protocol, verifying the read data, updating mainboard variable information when verification succeeds, comparing the model of a processor actually installed on the server with the model of the processor read from the memory, and if the models are matched, updating the mainboard variable information. If not, the processor is correct, and the server correctly loads and configures the peripheral settings of the processor according to the specified processor model in the memory, so that the problem that some mainboard functions cannot be normally used due to the fact that wrong configuration is executed when the server is started due to the fact that the processor models are not matched is solved.

The invention discloses an engine control-oriented worst execution analysis method, which comprises the following steps of: determining a processor model according to requirements of an engine control system, and selecting a static model and a worst execution time analysis tool corresponding to the processor model; analyzing the software architecture, confirming a task scheduling mode and a task time distribution scheme, and identifying the influence of the software architecture on the worst execution time; identifying target machine environment factors including internal hardware configuration and external hardware configuration of the processor, and compiling link parameters; based on an identification result, configuring target machine environment parameters in the worst execution time analysis tool, and importing a target code of to-be-analyzed software; in combination with an engine control function and an application scene, identifying a worst call tree path through static analysis, performing actual test on the final worst scene in a software and hardware integration test environment, and verifying whether the final worst scene meets time performance requirements and task time distribution in software requirements or not; if not, iteratively adjusting the software architecture or demand and then repeatedly executing the steps; the time security of the worst execution analysis result is confirmed through expert peer review, and it is ensured that all potential execution paths and extra time are covered; according to the method, the possible worst path can be identified more efficiently and accurately.

A routing data management method, apparatus and device, and a computer readable storage medium, the method comprising: calculating a storage address of routing data based on a processor model, the storage address being determined by a multi-objective optimization algorithm to separate the routing data from application software; and based on a routing template and routing data, generating a data file containing the storage address and a routing data line, so that a supplier end reads the storage address in the data file, writes the routing data into a specified area in a processor according to offset, and dynamically loads the routing data through address mapping, the data file is used for transmitting the routing data, the technical problem that the development cost and the management difficulty are increased due to the fact that the routing data is lack of effective management in related technologies is solved, unified management and control of the routing data by a main engine plant are achieved, the development workload of the main engine plant is reduced, and meanwhile the supplier adaptation cost is reduced.

The application relates to the technical field of software data processing, in particular to a method and system for upgrading home appliance control software. The method comprises the following steps: collecting the processor model, storage capacity, communication interface type and sensor state of the device to form hardware configuration information before starting the software upgrade process of the home appliance; judging whether the device hardware meets the running requirements of the preset new version software based on the hardware configuration information; if not, suspending the upgrade process and prompting the user with hardware incompatibility information; if yes, evaluating the storage space memory resources of the home appliance according to the hardware configuration information. The application realizes the efficiency of the home appliance control software upgrade through the memory resource optimization allocation technology, dynamic communication adjustment technology and data integrity recovery technology, thereby improving the overall stability of the home appliance upgrade process.

The present application relates to the technical field of communications. Provided are a decoding method for a low-density parity-check (LDPC) code, and an electronic device and a storage medium. The method comprises: acquiring a processor model of a user terminal, and matching system computing power information corresponding to the processor model; acquiring a first case decoding time corresponding to an LDPC decoding test case; and obtaining the maximum number of iterations on the basis of the system computing power information and the first case decoding time, and upon receiving data to be decoded, performing LDPC decoding on the basis of the maximum number of iterations. In the present application, the maximum number of iterations is cooperatively determined in view of two aspects, that is, system computing power information and a case decoding time, so as to perform LDPC decoding by means of the maximum number of iterations, such that the bit error rate of LDPC decoding is reduced to a certain extent while the requirements of a communication system for the communication performance are met, thereby reducing the number of retransmissions of data.

The invention relates to the technical field of chip verification, and provides a to-be-tested design verification method, device, equipment and medium, and the method comprises the steps: determining a target execution function from at least two execution functions in a verification environment based on management logic and arbitration logic in a C language direct programming interface (DPI)-C processor model; based on the target execution function, calling a homonymy function execution program corresponding to the target execution function from a program library; and verifying the to-be-tested design based on the homonymous function execution program. According to the method, the DPI-C processor model is used for replacing a real processor, the execution program is directly called according to the management logic and the arbitration logic of the DPI-C processor model, verification of the to-be-tested design is achieved, the situation that according to the specification of the execution program of the processor, the simulation speed is increased, and the iteration verification efficiency is improved is avoided.

The invention relates to the technical field of computers, and discloses a real-time task scheduling method and system oriented to embedded heterogeneous multi-core parallel computer.The method achieves reasonable distribution and real-time completion of parallel tasks through cooperation of a processor model, a task model and a task scheduling algorithm. And the resource utilization rate of the heterogeneous multi-core processor and the task execution flexibility are improved. Real-time task scheduling can be realized for more than three types of processors or accelerators on a built board-level integrated unified addressing shared memory processing architecture, and optimization targets comprise performance parameters of task completion time, operation energy consumption, resource utilization rate and task switching times. Meanwhile, the dynamic scheduling flexibility is achieved, different allocation strategies are used for different types of tasks by utilizing local queues and key tasks, and meanwhile, the tasks can be dynamically migrated according to the running states of the tasks and the performance condition of the system, so that load balancing of computing resources is achieved.

The invention discloses a real-time FADEC operating system transplantation method which comprises the following steps: determining a selected hardware processor model and a specific operating system kernel according to FADEC control software performance requirements; the method comprises the following steps: dividing interfaces of an application software layer and an operating system layer in FADEC control software, and modifying an initial starting part code of operating system software according to a selected processor model and an operating system kernel, including adjusting operating system kernel codes of different processor chips and software and hardware configuration in an initialization process; based on the defined interface, packaging the driving equipment before transplantation; the initialization code and the packaging interface function are combined, transplanted operating system software is obtained, an application layer interface is not changed, and the development process of the FADEC control software is completed; debugging and verifying power-on initialization, signal input and output, communication receiving and sending, task allowance and an abnormal response mechanism, and judging whether requirements are met or not according to verification results; the demand tracing error rate is reduced, and the research and development efficiency is improved.

The utility model belongs to the technical field of circuit boards of artificial intelligence equipment, in particular to a 100pin AI core board, which is characterized in that a plurality of pins are arranged on a side plate of a PCB (printed circuit board) of the 100pin AI core board, data interfaces formed by the pins comprise a microphone interface, a loudspeaker interface, a UART (universal asynchronous receiver / transmitter) interface and a GPIO (general purpose input / output) interface, the model of a processor on the PCB is RV1106G3, and the model of the processor on the PCB is RV1106G3. The processor has remarkable advantages in the aspects of computing power, image processing, coding, audio processing, low power consumption and the like, can meet operation and intelligent processing requirements when being used in the fields of security and protection equipment, image acquisition equipment, face recognition equipment and the like by being matched with different data interfaces, has good video data acquisition and processing functions, and can be widely applied to the fields of security and protection equipment, image acquisition equipment, face recognition equipment and the like. And various framework network models can be efficiently converted, and the requirements of intelligent equipment on data processing, image optimization and multi-camera cooperative work can be met.

The application discloses a communication performance test method and device and a storage medium, relates to the technical field of communication, and comprises the following steps: after network configuration is completed, a test link containing a server second-type processor, a server network port, a client second-type processor and a client network port is constructed according to the topological relationship of a peripheral component interconnect standard device corresponding to a host computer, and a single-machine graphics processor remote direct memory access test is performed on the test link. By adopting the technical scheme, the test can be completed on a single machine, the server and the client need not be set on different computing nodes, computing resources are saved, meanwhile, the test link need not be manually configured, and the processor model, the network card driver and the like of different computing nodes need not be uniformly configured, so that the configuration requirement is reduced.

The embodiment of the invention discloses a collaborative evaluation method for processor micro-architecture performance upper limit exploration and a related device, and the method comprises the steps: constructing various ideal micro-architecture components according to a collaborative process of a real processor model and an ideal model, and cooperatively evaluating the performance of a processor micro-architecture, the collaboration process comprises the following steps: the real processor model sends an instruction query and information request to the ideal model, wherein the request carries a memory address of a dynamic instruction; the ideal model executes the dynamic instruction according to the memory address in a normal working state to obtain a target value, and the target value serves as a response of the request and is returned to the real processor model; the real processor model executes the dynamic instruction in the execution stage to obtain an actual value; and verifying the target value and the actual value in the submission stage to obtain a verification result. By adopting the embodiment of the invention, the theoretical performance upper limit of a speculation execution technology such as value prediction can be accurately quantized, and the real performance bottleneck of the whole processor system integrated with the technology can be identified.

A method for automatic design of a processor and programming and simulation tools, comprising developing a single model of a processor from processor's specifications; providing the single model of the processor to an Electronic Design Automation tool, which automatically generates a hardware description and programming and simulation tools from the single processor model, and automatically determines validity of the single model of the processor, is disclosed. The method further comprises automatic verification of the designed processor.

The present application relates to a method, device, electronic device, and storage medium for measuring the computing power resources of a processor. The method includes: obtaining a plurality of preset test scenarios, each test scenario including the processor model to be tested, the number of video stream channels, the base library data corresponding to the number of test base libraries, and the number of processors allocated; obtaining a plurality of video files, and based on the number of video stream channels, inputting the plurality of video files into the test algorithms under each test scenario for algorithm operation testing, recording the corresponding test data obtained by running the test algorithms under each test scenario, and further obtaining the measurement result corresponding to the processor model to be tested. The measurement result includes the maximum number of channels supported by the processor model to be tested under different numbers of test base libraries and different numbers of processor allocations. Through the present application, the problem of how to balance the low cost and high performance of the computing power resources occupied by the AI algorithm is solved, and the balance between cost and performance is achieved on the premise of meeting the business requirements.

This application discloses a method for loading processor peripheral settings and a server system, relating to the field of server technology. The method reads the base address of a bidirectional two-wire serial bus and writes memory read / write capability enable and transmission configuration enable to a preset offset address space corresponding to the base address. Subsequently, it reads data from a specific address in memory using a multi-byte read method of the bidirectional two-wire serial bus protocol, verifies the read data, and updates motherboard variable information upon successful verification. It compares the actual processor model installed on the server with the processor model read from memory. If they match, the processor is correct, and the server will correctly load and configure the processor's peripheral settings according to the processor model specified in memory. This solves the problem of how to avoid incorrect configuration during server startup due to processor model mismatch, causing some motherboard functions to malfunction.

A system for automatically generating auto-scaling configurations for graphics processing unit (GPU) models is described. A provides users a platform to perform a load and performance (LnP) test on a model of a GPU of a computing device. The LnP test may result in a set of metrics associated with the GPU model. For example, the metrics may include throughput metrics (e.g., transactions per second (TPS)) and GPU utilization metrics. In some examples, the metrics may be based on a service level agreement (SLA), which may include latency, error rate, and GPU utilization requirements. Based on a scaling threshold determined from the metrics and a utilization requirement, the system may output an auto-scaling configuration for the GPU model. The GPU may operate using the auto-scaling configuration, where the auto-scaling configuration may enable the GPU model to scale up or scale down, for example, based on changes in traffic.