Instruction optimization processor for RSA encryption algorithm

A Technology of Instruction Optimization and Encryption Algorithm

Inactive Publication Date: 2012-09-12
SHANDONG UNIV
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Problems solved by technology

[0008] The first method is actually to optimize the algorithm itself, which can accelerate the RSA algorithm to a certain extent, but the acceleration effect is limited; the second method uses hardware acceleration, although the acceleration effect is more obvious, but this optimization method can be The scalability is weak, it occupies relatively more hardware resources, and it is difficult to combine with

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  • Instruction optimization processor for RSA encryption algorithm
  • Instruction optimization processor for RSA encryption algorithm
  • Instruction optimization processor for RSA encryption algorithm

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Embodiment Construction

[0041] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0042] figure 2 Among them, an instruction set processor model designed according to the extended instruction set, which realizes the above-mentioned extended instructions in hardware logic, so it can be used to accelerate the RSA encryption algorithm. The processor model mainly consists of register file 1, bus matrix 2, code memory 3, data memory 4, instruction pipeline 5, pipeline control component 6, pipeline fetching component 7, pipeline internal bus I, pipeline decoder component 9, and pipeline internal Composed of bus II10 and pipeline execution unit 11, the address space of data memory 4 is defined in the range of 0x0000-0x7FFF, with a size of 32K;

[0043] The code memory 3 address space is defined in the range of 0x8000-0xFFFF, with a size of 32Kbytes;

[0044] Register file 1 is mainly composed of 32 general-purpose registers, 1 fetch regi...

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Abstract

The invention relates to an instruction optimization processor for RSA encryption algorithm. The instruction optimization processor for RSA encryption algorithm adopts five extension instructions specially used for accelerating optimization on RSA encryption algorithm, and designs a special instruction processor model-RSA_ASIP corresponding to a new instruction set. The five extension instructions specially used for accelerating optimization on RSA encryption algorithm include getbit, shift_l, shift_r, muladd and muladd2 instructions, and the special instruction processor model-RSA_ASIP corresponding to the new instruction set consists substantially of a data memory, a code memory, a register file, a pipeline and a bus matrix. According to the RSA_ASIP processor designed by the invention, the execution of the RSA can be greatly optimized on the premise of ensuring flexibility and extensibility of software realization; through realization on RSA1024 and RSA2048, the instruction period is shortened by 64 percent on average compared with the realization on an ARM (Advanced RISC (Reduced Instruction-Set Computer) machines) processor, and the processor model after being subjected to instruction optimization can save resource consumption.

Description

technical field [0001] The invention relates to RSA encryption and decryption technology, in particular to instruction optimization and extended instruction set processor in RSA algorithm. Background technique [0002] RSA is currently the most influential public key encryption algorithm. It can effectively resist existing known cryptographic attacks and has been recommended by ISO as a public key data encryption standard. RSA can not only be used for data encryption, but also for digital signature. RSA is one of the necessary encryption algorithms for building a safe and reliable e-commerce platform and a trusted embedded computing environment (such as the Internet of Things). [0003] The RSA encryption algorithm is a block encryption algorithm. Firstly, the data packets to be encrypted are reasonably divided into blocks, and then each packet is encrypted block by block. The construction and implementation of the RSA cryptosystem are mainly divided into the following pro...

Claims

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Application Information

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IPC IPC(8): G06F9/30G06F9/318G06F9/38
Inventor 鞠雷王中波贾智平
Owner SHANDONG UNIV
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