Sbox generation instruction optimization method in AES (Advanced Encryption Standard) encryption algorithm and instruction set processor thereof

Abstract

The invention relates to an instruction optimization method for an Sbox generation process in an AES (Advanced Encryption Standard) encryption algorithm and a design of an instruction set processor model thereof. In order to accelerate the Sbox generation process in the AES algorithm, the invention designs three new extended instructions: (1) ifand(src1),(src2),(xor_src1),(xor_src2), for accelerating in-domain multiplication operation in the Sbox generation process; (2) getbit(dest)=(src),(bitpos), for accelerating bit-getting operation in the affine transformation process; and (3) xor5(dest)=(src1),(src2),(src3),(src4),(src5), for accelerating quinary exclusive-or operation in the affine transformation process. The three instructions are completed within one clock cycle; but in the traditional ARM (Advanced RISC Machines) processor, the three instructions respectively need multiple clock cycles. Thus, the new instructions achieve the accelerating effect. The invention also designs a special instruction processor model (SASIP) corresponding to the new instruction set according to the new extended instructions. The processor model realizes the extended instructions on hardware logic, thereby being a processor model specializing in AES-Sbox acceleration.

Description

technical field [0001] The invention relates to the encryption and decryption technology of AES, in particular to the instruction optimization method of the Sbox generation process in the AES encryption algorithm and the design of the instruction set processor. Background technique [0002] AES is the abbreviation of The Advanced Encryption Standard (Advanced Encryption Standard). It is a specification for encrypting electronic data published by the National Institute of Standards and Technology (NIST). It is the most widely used block cipher algorithm. The AES algorithm adopts a symmetric block cipher system, the key length can be 128 bits, 192 bits, and 256 bits respectively, and the block length is fixed at 128 bits. [0003] The encryption technique of AES uses an encryption key to perform a series of transformations to convert intelligible data called "plaintext" into incomprehensible data called "ciphertext". In the AES encryption and decryption algorithm, the non-li...

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Problems solved by technology

[0011] Using the method of hardware acceleration, although the acceleration effect is more obvious, this optimization method has weak scalability, occupies relatively more hardware resources, and is relatively difficult to combine with other modules in the program; optimize the algorithm itself The space is very limited, usually the improvement effect of optimization is not very obvious; and the third method not only reduces the execution code space and improves the execution speed of the algorithm through the design method of instruction set expansion optimization, but also is easy to implement and flexible in design. The performance is also relatively strong, and the requirements for hardware resources are much smaller than the first method, which is suitable for small-scale circuits

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