45 results about "Finite field multiplier" patented technology

A hardware-based finite field multiplier is used to scale incoming data from a disk drive and XOR the scaled data with the contents of a working buffer when performing resync, rebuild and other exposed mode read operations in a RAID or other disk array environment. As a result, RAID designs relying on parity stripe equations incorporating one or more scaling coefficients are able to overlap read operations to multiple drives and thereby increase parallelism, reduce the number of required buffers, and increase performance.

The invention designs a high-performance superscalar elliptic curve cryptographic processor chip shown as in the figure and relates to the technical fields of information security, encryption and decryption and chips. The chip designed by the invnetion adopts the modern processor superscalar technology,fully utilizes an instruction set to double the operational performance; a high-speed finite field multiplier greatly improves the computational efficiency, and properly solves the performance bottleneck of an elliptic curve cryptographic processor; the instruction set including the finite field arithmetic operation supported by the processor not only ensures that an elliptical curve cryptographic algorithm is more convenient to realize, but also makes necessary preparation for the future standardization; and the chip has a wide application prospect in the fields requiring information security, such as finance, communication and national defense.

The invention provides a finite field multiplier based on an irreducible trinomial. The multiplier comprises a controller, an input port, an output port, an exclusive or logic gate array, an and logic gate array, an irreducible trinomial matrix, a power modular arithmetic matrix, an and operation matrix, an exclusive or operation matrix and a multiplication operation matrix; the input port comprises a port for inputting a multiplication operand a(x), a port for inputting a b(x), a port for inputting the size of GF(2n) where the multiplication is located, and a port for inputting a clock signal; the output port comprises a port for outputting a multiplication result c(x), and a port for outputting feedback information about whether operation is within the multiplier operation range or not; the controller comprises a processor and an analyzer which are connected and is connected with the other components; the irreducible trinomial matrix stores the irreducible trinomial on different GF(2n); the and operation matrix stores the and operation results among bits of the a(x) and bits of the b(x). Compared with an existing multiplier, the finite field multiplier has the obvious speed advantage on multiplication on GF(2n) calculation.

This invention discloses a optimum design method for the finite field multiplier on the base of FPGA. This invention defines those logic functions which can be realized with a single 4-LUT into 7 styles, and it will follow some steps to realize the optimization for the finite field multiplier. Firstly, it figures out the matrix form of the finite field multiplier according to the generator polynomial and initialize the integration of middle variables. Secondly, it will repeatedly search for the common logic functions in the elements in the Matrix Z, bringing in a new middle variable, and it will use this new middle variable to represent the output variable of those logic functions, modifying the Matrix Z. Finally, it will find out preferred logic functions that can be realized by a single 4-LUT. Then those logic functions will be decomposed into a series of logic functions that can be realized by a single 4-LUT, and Matrix Z and the integration of middle variables will be modified. After all above, we finally get a optimized finite field multiplier on the base of FPGA. The advantages are short key route and time delay.

The present invention relates to a finite field multiplier used for implementing an encrypting algorithm circuit, thereby minimizing power consumption and circuit area in implementing the finite field multiplier with a LFSR (Linear Feedback Shift Register) structure. The Finite field multiplier of the present invention is an operator performing a modular operation on the multiplication result of two data represented on a polynomial basis in a Galois Field into an irreducible polynomial. The LFSR structure is a serial finite field multiplication structure, and has a merit over an array structure and a hybrid structure in application to systems that are limited in size and power due to its simplicity of circuits and also its capability of being implemented in a small size.

A general finite-field multiplier and the method of the same are disclosed for the operation of the finite-field multipliers of various specifications. In the multiplier, AND gates and XOR gates are used as primary components, and the inputs include two elements A and B to be multiplied and the coefficients of a variable polynomial p(x). This multiplier can be applied to the finite-field elements of different bit number. After all the coefficients of the A, B and p(x) are input, the values of a desired C can be obtained rapidly. Since the output values are parallel output, the application is very convenient. Furthermore, the multiplier can be used in the RS chip for different specifications.

The invention provides a finite field multiplier based on a binary tree structure. The finite field multiplier comprises an input port used for inputting the operand a(x) and the operand b(x) of a finite field GF(2<n>), an output port used for outputting the multiplying result c(x) of the operand a(x) and the operand b(x), and a binary tree structure used for executing the multiplying of GF(2<n>) with the operand a(x) and the operand b(x). The binary tree structure comprises n+1 layers, from top to bottom, the layers numbered from 1 to n include a left binary tree and a right binary tree, and the bottommost layer is the (n+1)th layer; each node of the (n+1)th layer is connected with three nodes of the nth layer. Multiplying of the finite field is achieved with the binary tree structure, the structure is simple, and the finite field multiplier has obvious speed advantages in multiplying of GF(2<n>) compared with an existing finite field multiplier, and can be widely applied to various engineering fields.

The invention discloses an RS decoder low in hardware complexity. Received code words are stored; syndrome polynomial coefficient of the code words is calculated by utilizing Horner rules and used for time division to realize a chien searching function, and an error position is determined; polynomial coefficient of the error position is iteratively calculated according to the syndrome polynomial coefficient through a decomposed non-inversion Berlekamp-Massey algorithm, and polynomial calculation of an error estimated value is realized according to syndrome polynomial and error position polynomial time division; an error value on the error position is calculated; corresponding code words in a synchronous FIFO are corrected according to the error position and the error value. According to an iBM algorithm in the form of decomposition, inversion operation is eliminated during iterative solving of error position polynomial, and iteration is performed through decomposition, so that number of finite field multipliers is reduced, hardware complexity is lowered, hardware resources are saved to a great extent, and area and power consumption of a decoder chip is reduced.

The invention provides an implementation method of a finite field multiplying unit with functions of detecting, correcting and locating an error. The finite field multiplying unit comprises an error locating unit, an error correction unit based on a redundant base, a finite field multiplication unit and an error detecting unit based on norm; and the finite field multiplying unit has the functions of detecting, correcting and locating the error. The finite field multiplying unit generated by the method has the function of locating the error so as to be convenient for dealing with hardware failure, and has the function of error correction so as to effectively resist the failure attack of an opponent.

The invention relates to an all-in-one irreducible polynomial based finite field multiplier which comprises a controller, an input control module, an output control module, a finite field multiplier and an operation module, wherein the controller is used for controlling and scheduling data transmission among the input control module, the output control module and the finite field multiplier; the input control module is used for inputting a multiplication operation number a(x) and a multiplication operation number b(x) when detecting that a finite field GF(2n) has an all-in-one irreducible polynomial; the finite field multiplier is used for calling the operation module to carry out finite field multiplication operation on the multiplication operation number a(x) and the multiplication operation number b(x) to obtain a multiplication operation result c(x); the operation module is used for implementing and logical operation, exclusive or logic operation and modular operation; the output control module is used for outing the multiplication operation result c(x). By adopting the multiplier, the operation efficiency of finite field multiplication is improved.

The invention provides a high-speed parallel RS encoding scheme for a consultative committee for space data system (CCSDS). The high-speed parallel RS encoder and an encoding method for the CCSDS are characterized in that the encoder is mainly composed of a finite field multiplying unit, a finite field adding device and a shifting register. Change of base is synthesized to a constant coefficient matrix of the finite field multiplying unit, a correctional coefficient matrix is produced, and the process of change of base is removed. The high-speed parallel RS encoder and the encoding method for the CCSDS has the advantages of being low in calculated amount, easy to achieve, capable of effectively reducing calculated amount of encoding and achieving complexity, and capable of improving encoding speed.

The invention relates to a fast arithmetic multi-bit serial pulse dual-base binary finite field multiplier, comprising an input end B, k PE modules, an FRRP module and an R3 module. The k PE modules are connected in series, the k PE modules pass through k cycles, in the first cycle, the input of A is that B is directly input, and the calculation result is restored and input into a temporary register C through the FRRP module; in the second cycle, the input of A is that B is input through the R3 module, the calculation result is also restored through the FRRP module, and is added to the calculation result of the first cycle and stored in the temporary register C; so, in the k cycle, the input of A is that B is input after passing through the R3 module for (k-1) times, the calculation result is restored through the FRRP module, added to the accumulation result of the previous (k-1) times and stored in the temporary register C, and the temporary register C outputs the result.

The invention relates to a scheme for solving a problem of parallel encoding of three kinds of reed-solomon (RS) codes in a china mobile multimedia broadcasting (CMMB) system and is characterized in that a parallel encoder of the multi-code rate RS codes of the system is manly composed of four parts including a shifting register, an eight-bit dual-input exclusive-or-gate, a summation array and product selectors. All finite field multiplying units share one 255 multiple-input exclusive-or-gate in the summation array. Each product selector selects eight outputs of the multiple-input exclusive-or-gate to form a result of the finite field multiplying units, and all product selectors completes parallel computation of the 64 finite field multiplying units simultaneously. A single encoder is compatible to three kinds of code rate, is simple in control logic, can greatly reduce resource needs on the premise of keeping encoding speed to be unchanged, and has the advantages of being low in cost, small in power dissipation and the like.

This invention discloses a Read-Solomon decoder key equation solution circuit. The aim is to avoid the long key path between the present registers, and the low working frequency of internal part of decoders. It includes R(x) shift register, Q(x) shift register, lambda(x) shift register, mu(x) shift register, the finite extent multiplier, the finite extent adder, the coefficient latch a0, b0 and a1. The characteristics are: it also includes the pipeline register C and E, the input end of the pipeline register C connects the finite extent adder A, the output end of the pipeline register C respectively connects the coefficient latch a1 and the finite extent multiplier C, the input end of the pipeline register E connects the finite extent adder C, the output end of the pipeline register E connects the finite extent multiplier G. Because increasing the number of the pipeline registers, the key path are shortened from '2XTmult+2XTadd' to 'Tmult+Tadd'. The highest working frequency of internal clock is 204.79MHz, and increases 63.6% of the present 133.33MHz.

The invention discloses a bit shift processing method based on RS (Reed-Solomon) coding blind synchronization. The bit shift processing method comprises the following steps of: receiving RS code words by using 66bit parallel data blocks; outputting in a 66bit parallel data block manner, and acquiring an RS code word syndrome; according to the syndrome result, judging whether the currently output bit position has a correct initial position of the RS code word or not; if not, shifting the output position of the 66bit parallel data block; if yes, obtaining the beginning of the next RS code word; and receiving the RS code word and decoding the RS code word. According to the method, the rate of finding the correct code word beginning in the received bit stream is improved, the calculation speed is improved, the calculation period is shortened, and the descrambling and decoding efficiency is greatly improved. The invention further discloses a bit displacement processing device based on RS coding blind synchronization, the structure is simple, the bit displacement processing device can be conveniently realized in finite field multipliers with different bit widths, and circuit integration is facilitated.

In an arrangement of the disclosed systems, devices, and methods, a codeword encoded with a first number of check symbols is received and asymmetrically processed according to a second number of check symbols, where the second number of check symbols is less than the first number of check symbols, to produce an error locator polynomial and an error evaluator polynomial. A derivative of the error locator polynomial is produced by outputting a first polynomial term and a second polynomial term, wherein the second polynomial term is a constant. The derivative of the error locator polynomial is produced using a variable finite-field multiplier and without use of a divider.

A composite finite field multiplier is disclosed. The multiplier includes a controller, an input port, an output port, a GF((2ⁿ)²) multiplier, a GF(2ⁿ) standard basis multiplier, and a GF(2ⁿ) look-up table multiplier; the controller is connected respectively to the input port, the output port, the GF((2ⁿ)²) multiplier, the GF(2ⁿ) standard basis multiplier and the GF(2ⁿ) look-up table multiplier; the GF((2ⁿ)²) multiplier is connected respectively to the GF(2ⁿ) standard basis multiplier and the GF(2ⁿ) look-up table multiplier. By using the GF((2ⁿ)²) multiplier, the GF(2ⁿ) standard basis multiplier and the GF(2ⁿ) look-up table multiplier, the multiplication of three operands is realized. Compared with the existing multiplier, the multiplier of the present invention has significant advantages in the speed of multiplying three operands over GF((2ⁿ)^m).