78 results about "Reed solomon decoder" patented technology

A pipelined digital data receiver for a cable TV headend which is capable of receiving DOCSIS 1.0 or 1.1 or advanced PHY TDMA or SCDMA bursts having programmable symbol rates and programmable modulation types as well as a host of other burst parameters such at Trellis code modulation on or off, scrambling on or off, various values for Reed-Solomon T number and codeword length. The receiver has an RF section to filter and digitize incoming RF signals. It also has an input section to detect impulse noise and do match filtering and despread SCDMA bursts. A timing recovery section recovers the symbol clock and detects the start of bursts and collisions. A rotational amplifier and equalizer calculate and track gain, phase and frequency offsets and correct symbols and calculates equalization coefficients. A decoder section decodes TCM and non TCM bursts, and a Reed-Solomon decoder section reconstructs RS codewords and uses them to error correct the payload data.

An error correcting Reed-Solomon decoder includes a syndrome calculator that calculates syndrome values. An error locator polynomial generator communicates with the syndrome calculator and generates an error locator polynomial. An error location finder communicates with at least one of the syndrome calculator and the error locator polynomial generator and generates error locations. An error values finder communicates with at least one of the syndrome calculator, the error location finder and the error locator polynomial generator and generates error values using an error value relationship that is not based on the traditional error evaluator polynomial. The error locator polynomial generator is an inversionless Berlekamp-Massey algorithm (iBMA), which calculates an error locator polynomial and a scratch polynomial. The error value relationship is based on the error locator polynomial and the scratch polynomial.

Transmitting data in a digital video broadcasting for handheld (DVB-H) receiver comprises a transport stream (TS) demultiplexer adapted to extract internet protocol (IP) datagrams from TS data packets; a packet identifier (PID) filter adapted to extract the TS data packets based on the PIDs of the TS data packets; a Multi Protocol Encapsulation-Forward Error Correction (MPE-FEC) random access memory (RAM) unit operatively connected to the TS demultiplexer; a Reed-Solomon decoder operatively connected to the MPE-FEC RAM unit; an IP to TS encapsulator operatively connected to the MPE-FEC RAM unit; a TS multiplexer operatively connected to each of the PID filter and the IP to TS encapsulator, wherein the TS multiplexer is adapted to combine both DVB-Terrestrial (DVB-T) and DVB-H TS data packets into a single combined TS data packet; and a host interface operatively connected to the TS multiplexer.

A Reed-Solomon decoder includes a Chien search circuit to receive an error location polynomial function, performs Chien search, and finds an error location; a Forney algorithm circuit to receives an error pattern polynomial function and find an error pattern; and, a seed generator circuit to indicates a seed value corresponding to a codeword length for the input data. A Chien search is performed to obtain and outputs exponential terms related to variables for the polynomials, wherein the Chien search is performed in the same computational direction as an order for the input data.

Encoded symbols of a concatenated convolutional-encoded and block encoded signal are presented to a conventional first stage of a concatenated decoder, comprising in sequence a soft metric generator, a Viterbi decoder, a first de-interleaver and a first block decoder such as a Reed-Solomon decoder. The encoded symbols are also presented to a delay chain to produce progressively delayed encoded symbols. Where an output block of the conventional decoder is indicated as being a valid codeword by the first block decoder, the bytes in this block are marked as being correct. These bytes that are known to be correct are then used after interleaving and serialisation as known bits input to a second stage of the decoder process operating on the delayed encoded symbols and incorporating a modified soft metric generator constrained by the known bits. This process can be extended to further iterations as required. A modified Viterbi decoder, which is also constrained by the known bits, may also be used in the second and subsequent iterative stages.

A signal detector to detect symbols in a read back signal. The signal detector includes a first detector to generate raw decisions as a function of the read back signal. A post processor identifies possible defects in the raw decisions. A selector selects a portion of the possible defects and generates modified decisions based upon correcting the portion of the possible defects. At least one signal decoder generates final decisions as a function of the modified and raw decisions. A decision block returns control to the selector in response to detecting excess errors in the final decisions.

A DVB-T receiver includes a channel equalizer, a metric assignment and demapping circuit, a Viterbi decoder and an outer Reed-Solomon decoder. The metric assignment and demapping circuit includes a soft-decision quantising arrangement which provides confidence values for the Viterbi decoder. The quantising arrangement receives a control input from channel state indication (CSI) measurement circuitry.

A further channel state indication is obtained on a symbol-by-symbol basis. This is compared an average obtained over a few symbols, to detect impulsive interference, and applied as part of the control for the soft-decision quantiser.

A signal derived from the further channel state indication is also applied to the erasures input of the Reed-Solomon decoder.

An error decoding system that comprises a first Reed-Solomon (RS) decoder that receives an encoded codeword and generates a decoded codeword. An inner code (IC) decoder checks the decoded codeword for uncorrected errors. A decoding control module communicates with the first RS decoder and the IC decoder, iteratively modifies a parameter of the first RS decoder if the IC decoder detects uncorrected errors in the decoded codeword, and instructs the first RS decoder to decode the encoded codeword again after modifying the parameter.

A Reed-Solomon decoder includes an inversionless Berlekamp-Massey algorithm (iBMA) circuit with a pipelined feedback loop. An error locator polynomial generator generates error locator polynomial values. A scratch polynomial generator generates scratch polynomial values. A discrepancy generator generates discrepancy values based on the error locator polynomial values and the scratch polynomial values. Multipliers used to generate the discrepancy values are also used to generate the error locator polynomial to reduce circuit area. A first delay circuit delays the discrepancy values. A feedback loop feeds back the delayed discrepancy values to the error locator polynomial generator and the scratch polynomial generator. An error location finder circuit communicates with the iBMA circuit and identifies error locations. An error value computation circuit communicates with at least one of the error location finder circuit and the iBMA circuit and generates error values.

A method and apparatus for identifying uncorrectable Reed-Solomon codewords in the presence of Reed-Solomon codewords which may have errors and erasures and otherwise be correctable.

A semiconductor memory device with an error checking/correction system includes a memory cell array. The error checking/correction system is capable of symbolizing data to a symbol, searching errors of data read from the memory cell array by solving equations with decoders representing a solution, correcting data based on the searched errors, and outputting the corrected data in parallel with the other process to the other data.

A Reed Solomon decoder utilizes re-configurable and re-usable components in a granular configuration which provides an upper array and a lower array of repeated Reconfigurable Elementary Units (REU) which in conjunction with a FIFO can be loaded with syndromes and correction terms to decode Reed Solomon codewords. The upper array of REUs and lower array of REUs handle the Reed Solomon decoding steps in a pipelined manner using systolic REU structures. The repeated REU includes the two registers, two Galois Field adders, a Galois Field multiplier, and multiplexers to interconnect the elements. The REU is then able to perform each of the steps required for Reed-Solomon decoder through reconfiguration for each step using the multiplexers to reconfigure the functions. In this manner, a reconfigurable computational element may be used for each step of the Reed-Solomon decoding process.

A random access memory (RAM) device for use in a high-speed pipelined Reed-Solomon decoder, a method of accessing the memory device, and a Reed-Solomon decoder having the memory device are provided. The memory device, which data is written to and read from at the same time during decoding of one frame of data, includes a random access memory (RAM) having a plurality of banks; and a control circuit for setting a first bank pointer, which selects a first bank among the plurality of banks, and a second bank pointer which selects a second bank among the plurality of banks, wherein the first and second bank pointers are set to banks with a predetermined offset every frame of data.

The invention claims a low hardware overhead Reed-Solomon decoder, comprising: a syndrome multinomial/chain search/error estimated value calculation multifunctional module, which realizes calculation of syndrome multinomial through algorithm S=((r<n-1>alphai-1+r<n-2>)alphai-1+...+r<1>)alphai-1+r<0> 1<=i<=2t, and is used for timely realizing functions of hidden search and error evaluation calculation etc; error position multinomial/error estimated value multinomial acquisition multifunctional module which has no need for iterating transfer inversion operation every time when performing solving using error position multinomial iteration algorithm through improved smooth Berlekamp-Massey algorithm so as to save the hardware resource, meanwhile, it can further timely realize acquisition of error position multinomial/error estimated value multinomial. The invention optimized decoding algorithm of Reed-Solomon decoder, reduces complexity of decoded hardware, greatly reduces the expenditure on hardware, and reduces the chip area and power consumption of the decoder.

The invention discloses an implementation method of a Reed-Solomon decoder. The Reed-Solomon decoder realizes solving on an error location polynomial and an error value polynomial by a controller, an arithmetic device and four shifting registers, and can decode a plurality of symbols of a Reed-Solomon code, thus achieving small and fixed delay time for decoding and regular structure.

A method and apparatus having a modified Reed-Solomon decoder is used for finding a specific code group used by a base station and the frame timing synchronization with the base station. The modified Reed-Solomon decoder uses a standard Reed-Solomon decoder and some reliability measurements computed from the received code word symbols. If the reliability of a received symbol is too low, this symbol is considered as erasure. By selecting code word symbols with higher reliabilities and erasing code word symbols with lower reliabilities, the symbol error probability is reduced and the performance is improved. Several modified Reed-Solomon decoders and a few decoding strategies are introduced in order to decode the received code word sequences with a power- and memory-effective method.