Reed-Solomon decoder with low hardware spending
A hardware overhead and decoder technology, applied in the field of Reed-Solomon decoders, can solve complex problems and achieve the effects of reducing chip area and power consumption, reducing hardware overhead, and optimizing hardware implementation complexity
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[0042] like figure 2 As shown, it is a structural block diagram of the Reed-Solomon decoder in the T-DMB receiving system of the present invention, including "syndrome polynomial / money search / error estimate calculation multifunctional module", "error position polynomial / error estimate Polynomial Calculation Multifunctional Module", Forney Algorithm Module and Error Correction Module. Among them, the "syndrome polynomial / Qian search / miscalculation multifunctional module" can realize syndrome calculation, chien search and miscalculation in time division under the control of the timing control module in the T-DMB receiving system. Function. The "error position polynomial / error estimated value polynomial calculation multifunctional module" can realize the iterative algorithm for solving the error position polynomial by using the improved non-inverse Berlekamp-Massey algorithm, and the modified algorithm does not need to call the inversion every iteration Computing has been grea...
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