56 results about "Modulo operation" patented technology

The disclosure discloses a method for routing subscriber traffic in a wireless network. The method comprising receiving one request at a service communication proxy (SCP) from at least one consumer node, determining if the received one request includes a subscription permanent identifier (SUPI) header. The method comprising extracting value of the SUPI header. The SUPI header includes a plurality of digits. The method comprising performing a modulo operation based on at least m number of digits of the SUPI header. The method comprising storing an index value corresponding to the at least m number of digits of the SUPI header in a memory. The method comprising calculating at least one network function instance value based on the stored index value and routing the received request to the calculated at least one network function instance to at least one provider node.

The invention belongs to the technical field of chip algorithms, and particularly relates to a circular array beam forming method and system based on a domestic FPGA. Comprising the following steps: receiving multiple paths of array element signals, and performing frequency mixing and filtering to obtain baseband I / Q data; the base band I / Q data is unpacked to be distributed and stored in a plurality of distributed memories in an FPGA (Field Programmable Gate Array) processing unit; the method comprises the following steps: reading baseband I / Q data of a plurality of channels and corresponding phase shift coefficients in parallel, and carrying out multiplication, accumulation, summation and modulo operation to generate data of a beam point; repeating the calculation step of generating the beam point data by updating the phase shift coefficient so as to generate beam domain data; reordering the calculated sequence of the beam domain data, and adjusting the output sequence of the beam domain data; the method has the advantages of being high in processing speed, high in anti-noise capacity and the like on the basis of meeting domestic substitution.

Provided are a method and an electronic device for performing convolutional neural network operations on a batch of input images using homomorphic encryption. The method includes: for each channel of the batch of the input images, grouping pixel values at the same location in the images included in the batch into a single vector, and encrypting the grouped vectors using a homomorphic encryption method to obtain a first ciphertext; for each channel and each coefficient of the ciphertext, grouping coefficients of the first ciphertext corresponding to all pixel locations to generate polynomials, and configuring the polynomials into a single matrix; multiplying the matrix by a polynomial matrix representing a convolution filter to obtain a result matrix, and performing a modulo operation on each element of the result matrix to generate an encrypted convolution operation result, the operation being performed on unencrypted matrices; and rearranging polynomial coefficients of the result matrix to generate a second ciphertext for the batch of the images after the convolution layer is applied, in which the second ciphertext is encrypted by the same homomorphic encryption method as the first ciphertext.

The application discloses an SRAM computing integrated NTT accelerator, a chip and electronic equipment, wherein the NTT accelerator comprises a computing integrated butterfly unit, an array decoder, a controller, a module approximation simple unit and an inter-column data router; the computing integrated butterfly unit is used for accelerating the NTT algorithm, realizing two kinds of butterfly operation operations, and storing input data of one-time butterfly operation and intermediate data generated in the calculation process; the array decoder and the controller are used for controlling the working state of each computing integrated butterfly unit when the butterfly operation is performed; the module approximation simple unit is used for processing the modulo operation of the data output after the multiplication of the multiplier is completed; the inter-column data router is connected with the input and output of each butterfly unit, is used for writing initial data into the butterfly unit, and is used for transmitting the calculation result of each stage to the corresponding unit, and preparing for the operation of the next stage. The application supports bit parallel operation, guarantees that the butterfly operation of one stage of NTT can be completed at the same time, and maximizes the operation efficiency.

The present disclosure provides a data processing method and device based on high-low carry instruction, electronic equipment and storage medium, which relates to the technical field of network security. The method comprises: obtaining a large integer product result using binary representation; dividing the large integer product result into a high-bit product result and a low-bit product result; performing a modulo operation on the low-bit product result to obtain a first modulo operation result; accumulating the highest bit of the first modulo operation result into a carry flag bit and performing a shift processing on the carry flag bit, wherein the highest bit of the first modulo operation result is set to zero; performing a modulo operation on the high-bit product result to obtain a second modulo operation result; and determining the modulo operation result of the large integer product result according to the result in the carry flag bit, the first modulo operation result and the second modulo operation result. The present disclosure optimizes the calculation process, reduces the number of instructions, improves the calculation efficiency, and improves the security by optimizing the carry flag bit cy reduction and avoiding while loop.

This application discloses a data query method, apparatus, electronic device, and computer-readable medium, relating to the field of big data processing technology. The method includes: receiving a data query request and obtaining a corresponding time identifier and database identifier; determining the corresponding number of partitions based on the database identifier, and then performing modulo operation based on the time identifier and the number of partitions to obtain a query partition identifier; responding to a change in the time identifier, determining a first historical partition from the historical partitions corresponding to the number of partitions and determining a second historical partition corresponding to the query partition identifier, and copying statistical information corresponding to the first historical partition to the second historical partition; generating a query statement based on the query partition identifier, accessing the second historical partition after copying the statistical information, and then executing the query statement to return query results. This achieves optimal query efficiency while improving the accuracy of data queries.

Disclosed in the embodiments of the present application are a signal processing method and apparatus, and a storage medium and a device. The method comprises: acquiring a delay instruction of a modulation signal, and determining the number of target delayed clock cycles corresponding to the delay instruction; on the basis of the number of target delayed clock cycles, performing an exact division operation on the number of standard clock cycles, and on the basis of an exact division operation result, generating at least one no-operation instruction; on the basis of the number of target delayed clock cycles, performing a modulo operation on the number of standard clock cycles, and on the basis of a modulo operation result, determining the number of delayed clock cycles of a preset length; after the at least one no-operation instruction, on the basis of the number of delayed clock cycles of the preset length, performing delay supplementation on the modulation signal, so as to generate a modulation signal that has been subjected to delay supplementation; and performing, in advance and by the number of standard clock cycles, signal demodulation on the modulation signal that has been subjected to delay supplementation, so as to obtain a signal demodulation result.

An equivalent multi-path routing method, apparatus and device, and a readable storage medium, the equivalent multi-path routing method comprising: based on available resource capacity of a network device and equivalent multi-path routing group capacity, calculating to obtain the total number of virtual nodes of an equivalent multi-path routing group, the equivalent multi-path routing group comprising a plurality of equivalent links; based on the total number of the virtual nodes and the bandwidth of each equivalent link, allocating a corresponding number of virtual nodes to each equivalent link; aiming at the data flow of the equivalent multipath routing group received by the network equipment, calculating through a Hash algorithm to obtain a data flow Hash value, and performing modulo operation on the data flow Hash value and the total number of the virtual nodes to obtain the virtual nodes corresponding to the data flow so as to forward the data flow through equivalent links corresponding to the virtual nodes; and when the fault of the equivalent link is detected, transferring and distributing the virtual node corresponding to the fault equivalent link to the remaining effective equivalent links. According to the invention, the probability of service interruption is greatly reduced.

The invention provides a Hash function construction method based on dynamic feedback quantum walk. The Hash function construction method comprises the following steps: step 1, realizing Hash function initialization based on dynamic feedback quantum walk; 2, realizing dynamic feedback quantum walking evolution; 3, obtaining the probability distribution of the final quantum state corresponding to each vertex on the two-dimensional grid points through projection measurement; and 4, executing a post-processing method, processing the probability of each vertex on the two-dimensional lattice points through interception and modulo operation, and connecting to obtain a final hash value. According to the method, the message is mapped into the initial parameter of the coin operator, so that the sensitivity of the hash function to the initial message is improved; meanwhile, a dynamic feedback mechanism is introduced to adjust coin operator parameters, the quantum walking evolution process is controlled to optimize quantum state probability distribution, and collision resistance and uniformity of a hash function are improved. According to the method, a high-safety and high-robustness scheme is provided for Hash function construction based on quantum walking.

The embodiment of the invention provides a data processing method and a related device, which are used for reducing intermediate data generated by performing operation on encrypted data based on modular operation and reducing the size of the encrypted data, so that the operation load of equipment is reduced, the data handling efficiency is improved, and the overall operation efficiency is improved. The method comprises the following steps: operating first ciphertext data and second ciphertext data by adopting an approximate operation algorithm to obtain a target reduction multiple which is used for replacing a reduction multiple obtained by operating the first ciphertext data and the second ciphertext data based on multiplication, the reduction multiple is used for controlling the numerical value of an output result obtained by performing modular operation based on data; and performing modular operation on the first ciphertext data and the second ciphertext data according to the target reduction multiple to obtain target ciphertext data.

The invention provides a multi-beam satellite pre-coding method and device, and the method comprises the following steps: carrying out the coding based on the signal-to-noise ratio data of a current receiving end, and obtaining a first coding vector; obtaining a modulation mode of the sending end to the current receiving end, mapping the modulation mode to obtain a corresponding mapping value, and encoding the mapping value to obtain a second encoding vector; constructing an input vector based on the first coding vector and the second coding vector, inputting the input vector to a preset ResMLP layer, the ResMLP layer being provided with a parameter generation network, a dynamic affine transformation layer, a linear layer and an adaptive gating residual connection layer, the parameter generation network outputting a scaling weight vector and a shift weight vector, and the shift weight vector outputting a shift weight vector; calculating an output embedded vector based on the input vector, the scaled weight vector, and the shifted weight vector; and inputting the output embedded vector into an output layer, and outputting a modulo operation frame size parameter through an activation function layer of the output layer.

This invention discloses a method and system for measuring and detecting micro-time-series data based on a programmable switch. The method specifically includes: determining whether a new time period has begun based on the arrival time of the data packet and the truncation timestamp within the bucket; triggering an asynchronous update operation when a new time period is determined, extracting statistical values ​​from the previous period, updating the truncation timestamp within the bucket, and resetting the counter; storing statistical values ​​in a sliding window slot of a two-dimensional circular queue based on the modulo operation result of the flow key hash and the current timestamp in a storage module to construct a time-series data sequence for each flow; obtaining the time-series data sequence from the storage module and calculating time-series statistical features within the data plane; inputting the time-series statistical features and packet-level features into a machine learning model deployed on the data plane for inference, and outputting anomaly detection results. This invention overcomes hardware constraints, completing the generation, storage, and analysis of time-series data in a closed loop within the data plane, improving the real-time performance and accuracy of network anomaly detection.

The embodiment of the invention provides a data processing method and device, a processor, computer equipment, a medium and a program, and the processor comprises a decoder which responds to a microcode of an elliptic curve cryptographic algorithm and decodes a plurality of instructions, and at least one part of the instructions are basic instructions; the logical operation unit comprises a basic instruction operation subunit used for operating the basic instruction; wherein part or all of the basic instruction is a modular operation instruction obtained by taking a prime number p as a modulus. According to the embodiment of the invention, the complexity and deployment cost of hardware operation can be remarkably reduced.

The invention discloses a sequence seed recovery method, a computing device, a storage medium and a product, and belongs to the technical field of communication. The sequence seed recovery method comprises the following steps: acquiring cache data of a pseudo-random binary sequence; target operation is carried out on each bit of data in the cached data of the pseudo-random binary sequence to obtain operation results, the operation results are accumulated to obtain an accumulation result, and the target operation comprises modulo operation and / or XOR operation; the accumulation result comprises the first number of accumulated values, the method does not need to depend on a local pseudo-random binary sequence, is high in independence, and can directly obtain the pseudo-random binary sequence seed by carrying out operation accumulation and judgment through the obtained cache data of the pseudo-random binary sequence; correlation operation is not needed, power consumption is low, the operation efficiency of the rapid recovery process of the pseudo-random binary sequence seeds can be improved, and therefore the detection capacity can be improved.

A parallel multiplier for the Saber algorithm comprises a coefficient memory, two parallel pre-adding circuits, three parallel multiplication circuits and a post-adding circuit. The coefficient memory, the two parallel pre-adding circuits, the three parallel multiplication circuits and the post-adding circuit adopt a divide-and-conquer strategy, the two parallel pre-adding circuits perform parallel computation, and the three parallel multiplication circuits perform parallel computation, such that the computation time of modulo multiplication is shorted; the modulo operation of non-prime numbers is realized by limiting the bit width, such that the constraint that the modulus is a prime number is avoided; and the Karatsuba algorithm is called once, such that extra circuit area expenditure is reduced. Thus, the parallel multiplier for the Saber algorithm is implemented by hardware, low in computation complexity, not limited by the constraint that the modulus is a prime number, and low in circuit area expenditure.

An electronic system includes system memory having N interleaved channels, where N is not a power of two. A hardware-implemented method for the electronic system includes receiving a request to access the system memory, the request including an M-bit address; and processing the address to calculate a modulo N of the address without performing division-by-N. The modulo N of the address is calculated as [Σi αi mod N*2b<sub2>i < / sub2>mod N]mod N, where Σi αi*2b<sub2>i < / sub2>represents the M-bit address, ai is an ith word in the address, and 2b<sub2>i < / sub2>is a power of two associated with the ith word. The method further includes using the modulo N of the address as an offset to determine which of the N interleaved channels to access.

The invention relates to the technical field of data processing, in particular to a method, a device and equipment for replacing and desensitizing Chinese name fields. The method comprises the following steps: randomly arranging common Chinese characters of names to form a one-to-many mapping basic mapping table which comprises an original Chinese character set and at least one mapping Chinese character set; calculating the hash value of a real name to be desensitized, and then performing modulo operation to obtain the offset of each Chinese character; and matching each Chinese character in the real name in the original Chinese character set to obtain the corresponding desensitized Chinese character to combine into a final desensitized name. According to the embodiment of the invention, the relevance of the Chinese name field is ensured to the greatest extent, and the data analysis and mining application after desensitization is not influenced. Meanwhile, it is guaranteed that the algorithm is irreversible and high in safety, and data leakage in a larger range cannot be caused under the condition that the mapping relation between part of real data and desensitized data is leaked.

The present application provides a sequence seed recovery method, a computing device, a storage medium, and a product. The sequence seed recovery method comprises: acquiring cached data of a pseudo-random binary sequence; performing a target operation on each bit of data in the cached data of the pseudo-random binary sequence to obtain an operation result, and accumulating the operation results to obtain an accumulated result, wherein the target operation comprises a modulo operation and / or an exclusive OR operation; and performing decision on the basis of the accumulated result to obtain a pseudo-random binary sequence seed, wherein the accumulated result comprises a first number of accumulated values.

This disclosure relates to methods and systems for selecting secure prime numbers for a finite field Diffie-Hellman key exchange. A method for Diffie-Hellman key exchange includes: selecting a field size p in the format p = hq + 1, where q is a prime number of 1 plus factorial b such that q = (b! + 1), and h is a cofactor of a prime number such that p = hq + 1; selecting a generator integer g whose order modulo p is a prime number q or divisible by q; selecting a private key x; and calculating the public key g by applying arithmetic modulo operations on the prime field size p using the power of the private key x raised to the power of the generator g. x mod p; Sends the public key g to the communicating party. x mod p; Receive the second public key B from the communicating party. The second public key B includes the second private key y raised to the power of g, in the form g y The second private key y is chosen by the communicating party; and the key B is created from the received second public key B by applying arithmetic modulo operation on the size p of the prime field, by raising the second public key B to the power of the private key x. x .

A method for performing encoding on the basis of a parity check matrix of a low density parity check code according to the present embodiment comprises the steps of: generating a parity check matrix by a terminal, wherein the parity check matrix corresponds to a characteristic matrix, each component of the characteristic matrix corresponds to a shift index value determined through a modulo operation between a corresponding component in a basic matrix and Zc, which is a lifting value, and the basic matrix is a 42 x 52 matrix; and performing encoding of input data, by the terminal, using the parity check matrix, wherein the lifting value is associated with the length of the input data.

Disclosed are a method and apparatus for performing random access in a wireless communication system. A method by which a terminal performs a random access procedure in a wireless communication system, according to an embodiment of the present disclosure, comprises the steps of: transmitting a random access preamble to a network from a slot based on a subcarrier spacing (SCS) exceeding a predetermined threshold value; monitoring downlink control information (DCI) based on a specific radio network temporary identifier (RNTI) corresponding to the random access preamble; and receiving a downlink data channel from the network, on the basis of scheduling information included in the DCI, wherein the specific RNTI is determined on the basis of a value derived via a modulo operation using 2M−K as a divisor, M is associated with an offset value for distinguishing the type of the random access procedure, and K may be an integer exceeding 12.

The invention belongs to the technical field of wireless communication, and particularly relates to a distributed identity endogenous security management method based on a multilayer architecture and application thereof, and the method comprises the following steps: respectively obtaining certificates of a user network and hardware, and respectively calculating abstracts of the network and the hardware based on the obtained certificates by using an SHA-256 algorithm; after the abstracts of the network and the hardware are subjected to XOR entanglement, salt splicing, Hash mapping and modular operation are sequentially adopted for processing, and an identity private key is generated; based on an elliptic curve algorithm, taking the generated identity private key as a scalar, and performing scalar multiplication with the base point to generate an identity public key; the public key and the network characteristic factor are subjected to secondary cascade hash to serve as specific content of the identifier, and a decentralized identifier DID is obtained; and packaging the identity information in the JSON format, declaring that the generation of the identity is bound with the IMSI, and jointly outputting the decentralization information and the identity information as the identity information of the user. According to the invention, the whole-network uniqueness of the identity of the mobile communication entity is realized.

This invention discloses a data transmission integrity verification system and method based on a polynomial ring, relating to the field of data security technology. It includes two entities, User A and User B. User A sends data, and User B receives data. Both User A and User B include a symmetric key store, an integrity verification module, and a data transmission module. The data transmission module receives binary stream data and converts it into elements of a polynomial ring. Simultaneously, it converts the verified data back into a binary stream and sends it. The integrity verification module sequentially selects keys from the symmetric key store and performs data integrity verification using polynomial modulo operations. This invention differs from conventional cryptography, which is designed based on mathematical problems and is vulnerable to cryptanalysis based on artificial intelligence and quantum computing. It relies solely on mathematical principles to design the integrity verification mechanism, using the random selection of the basis of a polynomial ring for data integrity verification to resist various cryptographic attacks based on artificial intelligence and quantum computing.

The embodiment of the invention discloses a signal processing method and device, a storage medium and equipment, and the method comprises the steps: obtaining a delay instruction corresponding to a modulation signal, and determining a target delay clock cycle number corresponding to the delay instruction; performing integer division operation on the standard clock cycle number according to the target delay clock cycle number, and generating a preset number of null operation instructions according to an integer division operation result; performing modulo operation on the standard clock cycle number based on the target delay clock cycle number, and determining a delay clock cycle number with a preset length according to a modulo operation result; after a preset number of null operation instructions, performing delay supplement on the modulation signal according to a delay clock period number with a preset length, and generating a modulation signal after delay supplement; and carrying out signal demodulation on the modulation signal after delay supplement in advance of the standard clock cycle number to obtain a signal demodulation result. The clock period number of signal processing is reduced, the calibration time of the quantum gate is further shortened, and the calibration efficiency of the quantum gate is improved.

This application provides a system code-based encryption method, apparatus, and device. The method includes: acquiring the total number of bits in the data to be encrypted and a preset transfer matrix; wherein the preset transfer matrix is ​​used to indicate the mapping relationship between the operation result of the system code division circuit in the first clock cycle, the operation result of the division circuit in the second clock cycle, and the characters in the data to be encrypted received by the division circuit in the first clock cycle; determining the remainder of the data to be encrypted based on the total number of bits, the data to be encrypted, and the preset transfer matrix; the remainder is used to indicate the remainder after performing a modulo operation between the data to be encrypted and the generator polynomial of the system code; and determining the system code encryption result of the data to be encrypted based on the remainder and the data to be encrypted. By acquiring the preset transfer matrix, the total number of bits in the data to be encrypted, and the data to be encrypted to determine the encryption result, the problem of the long time consumption in determining the remainder using a division circuit in related technologies can be avoided.

This application discloses a calculator and its related methods. The calculator is used to accelerate the calculation of 2 N Number theory transformation of 2D polynomials. The calculator includes a first coefficient memory, a second coefficient memory, a twitch factor memory, multiple processing units, and a data flow controller. The data flow controller is used to control the multiple processing units to access the addresses of the first and second coefficient memories and the twitch factor memory when the processing units perform multiple coefficient operations. In odd-numbered coefficient operations, 2 M Each processing unit executes 2 (N‑M‑1) The first calculation program reads coefficients from the first coefficient memory and performs modulo operations, and then executes 2... (N‑M‑1) The first write operation writes the output coefficients generated by the calculation to the second coefficient memory. In even-numbered coefficient operations, 2 M Each processing unit executes 2 (N‑M‑1) The second calculation program reads coefficients from the second coefficient memory and performs modulo operations, and executes 2 (N‑M‑1) The second write procedure writes the output coefficients generated by the operation into the first coefficient memory.

Embodiments of the present application disclose a picture compression method, device, computer equipment and storage medium. The method comprises: performing a modulo operation on a picture to be compressed to obtain original data; transforming the original data and storing the transformed data in different buffer areas, and counting non-repeated data statistics in each buffer area; determining the buffer area with the minimum non-repeated data statistics as a target buffer area, generating a color data table according to the non-repeated data in the target buffer area; generating an index table according to the target buffer area and the color data table; and compressing the index table to obtain a compressed index table. Through the method of the embodiments of the present application, the picture can be losslessly compressed while occupying a small space during compression.

The application relates to the field of digital signal processing, in particular to a symbol synchronization method suitable for a wired communication system of THP, a feedforward transversal filter FFE is used to pre-process baseband receiving symbols, phase discrimination processing is carried out on the symbols processed by the FFE, in the phase discrimination processing part, an estimated value of the current receiving symbol is obtained through modulo operation and decision, an error between the receiving symbol and the estimated value is calculated, threshold comparison and compensation are carried out on the error, sampling phase deviation information is obtained by correlating the compensated error with an expected symbol; finally, the sampling deviation information is processed by using a direct path and an integral path of a loop filter, and is used for controlling a numerically controlled oscillator NCO to adjust a next sampling position. The sampling phase error information is processed in a linear domain, the influence of nonlinear modulo operation of THP on the phase discrimination algorithm is avoided, the stability of the symbol synchronization method is improved, and low calculation complexity is maintained.

The invention discloses an encryption and decryption method compatible with a shallow compression JPEG XS standard based on space scrambling, the encryption method comprises row scrambling, column scrambling, color scrambling and pixel scrambling, the row scrambling is to use a hash function to carry out modulo operation on a key stream, the modulus is used as a key, and the minimum coding unit row scrambling is carried out on an input image; column scrambling is carried out according to the arrangement of Haar wavelet transform coefficients; the color scrambling refers to performing color space scrambling on different coding units; pixel scrambling is to perform chaotic scrambling and symbol flipping operation on coefficients before wavelet transform. According to the data stream trend of the JPEG XS standard, the compression encryption-decryption method compatible with the JPEG XS standard is provided, so that the anti-interference performance in the compression process is improved, compression is achieved, the safety of image content is protected, and the method plays a key role in the safety of video data in the aspects of transmission and storage.

The application discloses a JPEG image encryption method based on coefficient grouping encryption, which comprises the following steps: obtaining original DC coefficient difference entropy coding and AC coefficient entropy coding of all blocks; predicting the DC coefficient to obtain a DC prediction error value; obtaining and using an initial key to group and scramble and encrypt AC coefficients containing complete AC coefficient entropy coding; extracting image features; obtaining and using an adaptive key related to image content to scramble and encrypt blocks without DC coefficients to obtain encrypted AC coefficients; using a quantization table of a to-be-encrypted JPEG image and the adaptive key to normalize and encrypt the DC prediction error value through modulo operation to obtain encrypted DC coefficients; and performing entropy coding on the encrypted DC coefficients and AC coefficients to obtain an encrypted image. The application improves the generality of encryption and decryption, and improves the change rate of NCC, EAC and PLZ features by scrambling and encrypting different types of AC coefficient groups.