80 results about "Modulo operation" patented technology

A computer-implemented method comprising receiving a digital media signal from a creator; segmenting the media signal into sequential discrete segments; selecting a subset of the sequential discrete segments; iteratively, for each discrete segment, (i) generating a segment vector, (ii) generating an encrypted metadata vector based on media signal metadata, (iii) combining the segment vector and the metadata vector, (iv) applying a modulo operation to the combined vector to obtain a hidden pattern vector, (v) generating an encrypted creator vector, (vi) subtracting the hidden pattern vector from the creator vector to obtain a signature vector, (vii) modifying selected values in the discrete segment, based on the signature vector, to obtain a modified discrete segment; and outputting a modified version of the media signal comprising all of the modified discrete segments.

Disclosed are methods, systems, devices, circuits. and other implementations, including a method for error identification and correction that includes obtaining from a memory device coded input data, the coded input data previously encoded by multiplying a source data element by a pre-determined multiplier, and stored in the memory device, and performing a decoding operation on the coded input data obtained from the memory device, with the decoding operation including at least a modulo operation, to derive a resultant decoded data element and a remainder portion. The method further includes determining whether the coded input data includes a corrupted portion based on a value of the remainder portion.

The disclosure discloses a method for routing subscriber traffic in a wireless network. The method comprising receiving one request at a service communication proxy (SCP) from at least one consumer node, determining if the received one request includes a subscription permanent identifier (SUPI) header. The method comprising extracting value of the SUPI header. The SUPI header includes a plurality of digits. The method comprising performing a modulo operation based on at least m number of digits of the SUPI header. The method comprising storing an index value corresponding to the at least m number of digits of the SUPI header in a memory. The method comprising calculating at least one network function instance value based on the stored index value and routing the received request to the calculated at least one network function instance to at least one provider node.

The invention belongs to the technical field of chip algorithms, and particularly relates to a circular array beam forming method and system based on a domestic FPGA. Comprising the following steps: receiving multiple paths of array element signals, and performing frequency mixing and filtering to obtain baseband I / Q data; the base band I / Q data is unpacked to be distributed and stored in a plurality of distributed memories in an FPGA (Field Programmable Gate Array) processing unit; the method comprises the following steps: reading baseband I / Q data of a plurality of channels and corresponding phase shift coefficients in parallel, and carrying out multiplication, accumulation, summation and modulo operation to generate data of a beam point; repeating the calculation step of generating the beam point data by updating the phase shift coefficient so as to generate beam domain data; reordering the calculated sequence of the beam domain data, and adjusting the output sequence of the beam domain data; the method has the advantages of being high in processing speed, high in anti-noise capacity and the like on the basis of meeting domestic substitution.

The invention provides a data processing method and device, electronic equipment, a chip and a storage medium, and relates to the technical field of data processing.The method comprises the steps that a first index of to-be-decoded data in an index set is determined; obtaining an initial interleaving address associated with the first index; and determining an interleaving code associated with the first index based on the initial interleaving address and a preset row and column operation rule. Therefore, the interleaving code associated with the first index is calculated through the first index and the row and column operation rule, the use condition of modular operation can be reduced through row and column operation, consumption of calculation resources is avoided, efficiency can be well improved under the condition of high speed or large data flow, and in some low-power-consumption or resource-limited environments, the interleaving code associated with the first index is calculated through the interleaving code associated with the first index. Power consumption and performance requirements can be balanced, and the reliability of a communication system is improved.

Provided are a method and an electronic device for performing convolutional neural network operations on a batch of input images using homomorphic encryption. The method includes: for each channel of the batch of the input images, grouping pixel values at the same location in the images included in the batch into a single vector, and encrypting the grouped vectors using a homomorphic encryption method to obtain a first ciphertext; for each channel and each coefficient of the ciphertext, grouping coefficients of the first ciphertext corresponding to all pixel locations to generate polynomials, and configuring the polynomials into a single matrix; multiplying the matrix by a polynomial matrix representing a convolution filter to obtain a result matrix, and performing a modulo operation on each element of the result matrix to generate an encrypted convolution operation result, the operation being performed on unencrypted matrices; and rearranging polynomial coefficients of the result matrix to generate a second ciphertext for the batch of the images after the convolution layer is applied, in which the second ciphertext is encrypted by the same homomorphic encryption method as the first ciphertext.

The application discloses an SRAM computing integrated NTT accelerator, a chip and electronic equipment, wherein the NTT accelerator comprises a computing integrated butterfly unit, an array decoder, a controller, a module approximation simple unit and an inter-column data router; the computing integrated butterfly unit is used for accelerating the NTT algorithm, realizing two kinds of butterfly operation operations, and storing input data of one-time butterfly operation and intermediate data generated in the calculation process; the array decoder and the controller are used for controlling the working state of each computing integrated butterfly unit when the butterfly operation is performed; the module approximation simple unit is used for processing the modulo operation of the data output after the multiplication of the multiplier is completed; the inter-column data router is connected with the input and output of each butterfly unit, is used for writing initial data into the butterfly unit, and is used for transmitting the calculation result of each stage to the corresponding unit, and preparing for the operation of the next stage. The application supports bit parallel operation, guarantees that the butterfly operation of one stage of NTT can be completed at the same time, and maximizes the operation efficiency.

The present disclosure provides a data processing method and device based on high-low carry instruction, electronic equipment and storage medium, which relates to the technical field of network security. The method comprises: obtaining a large integer product result using binary representation; dividing the large integer product result into a high-bit product result and a low-bit product result; performing a modulo operation on the low-bit product result to obtain a first modulo operation result; accumulating the highest bit of the first modulo operation result into a carry flag bit and performing a shift processing on the carry flag bit, wherein the highest bit of the first modulo operation result is set to zero; performing a modulo operation on the high-bit product result to obtain a second modulo operation result; and determining the modulo operation result of the large integer product result according to the result in the carry flag bit, the first modulo operation result and the second modulo operation result. The present disclosure optimizes the calculation process, reduces the number of instructions, improves the calculation efficiency, and improves the security by optimizing the carry flag bit cy reduction and avoiding while loop.

The present invention discloses a method for generating a pseudo-random sequence for integer data in signal processing. The seed can be arbitrarily selected within the range of integer data. The sequence iteration algorithm does not use multiplication and modulo operations, and the sequence data traverses the entire data range. The present invention simplifies the linear congruence algorithm, making the generation speed of the pseudo-random sequence faster and more resource-saving, while still retaining the characteristic of a long output sequence period. The present invention is applicable to various integer data types and can also be extended to any hexadecimal data with the number of bits n≥8. Pseudo-random sequences play an important role in information security fields such as multiple access communication, encryption algorithms, data scrambling, signal synchronization, error code testing, security protocols, digital watermarking, and cryptographic chips.

This application discloses a data query method, apparatus, electronic device, and computer-readable medium, relating to the field of big data processing technology. The method includes: receiving a data query request and obtaining a corresponding time identifier and database identifier; determining the corresponding number of partitions based on the database identifier, and then performing modulo operation based on the time identifier and the number of partitions to obtain a query partition identifier; responding to a change in the time identifier, determining a first historical partition from the historical partitions corresponding to the number of partitions and determining a second historical partition corresponding to the query partition identifier, and copying statistical information corresponding to the first historical partition to the second historical partition; generating a query statement based on the query partition identifier, accessing the second historical partition after copying the statistical information, and then executing the query statement to return query results. This achieves optimal query efficiency while improving the accuracy of data queries.

Disclosed in the embodiments of the present application are a signal processing method and apparatus, and a storage medium and a device. The method comprises: acquiring a delay instruction of a modulation signal, and determining the number of target delayed clock cycles corresponding to the delay instruction; on the basis of the number of target delayed clock cycles, performing an exact division operation on the number of standard clock cycles, and on the basis of an exact division operation result, generating at least one no-operation instruction; on the basis of the number of target delayed clock cycles, performing a modulo operation on the number of standard clock cycles, and on the basis of a modulo operation result, determining the number of delayed clock cycles of a preset length; after the at least one no-operation instruction, on the basis of the number of delayed clock cycles of the preset length, performing delay supplementation on the modulation signal, so as to generate a modulation signal that has been subjected to delay supplementation; and performing, in advance and by the number of standard clock cycles, signal demodulation on the modulation signal that has been subjected to delay supplementation, so as to obtain a signal demodulation result.

An equivalent multi-path routing method, apparatus and device, and a readable storage medium, the equivalent multi-path routing method comprising: based on available resource capacity of a network device and equivalent multi-path routing group capacity, calculating to obtain the total number of virtual nodes of an equivalent multi-path routing group, the equivalent multi-path routing group comprising a plurality of equivalent links; based on the total number of the virtual nodes and the bandwidth of each equivalent link, allocating a corresponding number of virtual nodes to each equivalent link; aiming at the data flow of the equivalent multipath routing group received by the network equipment, calculating through a Hash algorithm to obtain a data flow Hash value, and performing modulo operation on the data flow Hash value and the total number of the virtual nodes to obtain the virtual nodes corresponding to the data flow so as to forward the data flow through equivalent links corresponding to the virtual nodes; and when the fault of the equivalent link is detected, transferring and distributing the virtual node corresponding to the fault equivalent link to the remaining effective equivalent links. According to the invention, the probability of service interruption is greatly reduced.

The invention provides a Hash function construction method based on dynamic feedback quantum walk. The Hash function construction method comprises the following steps: step 1, realizing Hash function initialization based on dynamic feedback quantum walk; 2, realizing dynamic feedback quantum walking evolution; 3, obtaining the probability distribution of the final quantum state corresponding to each vertex on the two-dimensional grid points through projection measurement; and 4, executing a post-processing method, processing the probability of each vertex on the two-dimensional lattice points through interception and modulo operation, and connecting to obtain a final hash value. According to the method, the message is mapped into the initial parameter of the coin operator, so that the sensitivity of the hash function to the initial message is improved; meanwhile, a dynamic feedback mechanism is introduced to adjust coin operator parameters, the quantum walking evolution process is controlled to optimize quantum state probability distribution, and collision resistance and uniformity of a hash function are improved. According to the method, a high-safety and high-robustness scheme is provided for Hash function construction based on quantum walking.

The embodiment of the invention provides a data processing method and a related device, which are used for reducing intermediate data generated by performing operation on encrypted data based on modular operation and reducing the size of the encrypted data, so that the operation load of equipment is reduced, the data handling efficiency is improved, and the overall operation efficiency is improved. The method comprises the following steps: operating first ciphertext data and second ciphertext data by adopting an approximate operation algorithm to obtain a target reduction multiple which is used for replacing a reduction multiple obtained by operating the first ciphertext data and the second ciphertext data based on multiplication, the reduction multiple is used for controlling the numerical value of an output result obtained by performing modular operation based on data; and performing modular operation on the first ciphertext data and the second ciphertext data according to the target reduction multiple to obtain target ciphertext data.

The invention provides a multi-beam satellite pre-coding method and device, and the method comprises the following steps: carrying out the coding based on the signal-to-noise ratio data of a current receiving end, and obtaining a first coding vector; obtaining a modulation mode of the sending end to the current receiving end, mapping the modulation mode to obtain a corresponding mapping value, and encoding the mapping value to obtain a second encoding vector; constructing an input vector based on the first coding vector and the second coding vector, inputting the input vector to a preset ResMLP layer, the ResMLP layer being provided with a parameter generation network, a dynamic affine transformation layer, a linear layer and an adaptive gating residual connection layer, the parameter generation network outputting a scaling weight vector and a shift weight vector, and the shift weight vector outputting a shift weight vector; calculating an output embedded vector based on the input vector, the scaled weight vector, and the shifted weight vector; and inputting the output embedded vector into an output layer, and outputting a modulo operation frame size parameter through an activation function layer of the output layer.

This invention discloses a method and system for measuring and detecting micro-time-series data based on a programmable switch. The method specifically includes: determining whether a new time period has begun based on the arrival time of the data packet and the truncation timestamp within the bucket; triggering an asynchronous update operation when a new time period is determined, extracting statistical values ​​from the previous period, updating the truncation timestamp within the bucket, and resetting the counter; storing statistical values ​​in a sliding window slot of a two-dimensional circular queue based on the modulo operation result of the flow key hash and the current timestamp in a storage module to construct a time-series data sequence for each flow; obtaining the time-series data sequence from the storage module and calculating time-series statistical features within the data plane; inputting the time-series statistical features and packet-level features into a machine learning model deployed on the data plane for inference, and outputting anomaly detection results. This invention overcomes hardware constraints, completing the generation, storage, and analysis of time-series data in a closed loop within the data plane, improving the real-time performance and accuracy of network anomaly detection.

The embodiment of the invention provides a data processing method and device, a processor, computer equipment, a medium and a program, and the processor comprises a decoder which responds to a microcode of an elliptic curve cryptographic algorithm and decodes a plurality of instructions, and at least one part of the instructions are basic instructions; the logical operation unit comprises a basic instruction operation subunit used for operating the basic instruction; wherein part or all of the basic instruction is a modular operation instruction obtained by taking a prime number p as a modulus. According to the embodiment of the invention, the complexity and deployment cost of hardware operation can be remarkably reduced.

The invention discloses a sequence seed recovery method, a computing device, a storage medium and a product, and belongs to the technical field of communication. The sequence seed recovery method comprises the following steps: acquiring cache data of a pseudo-random binary sequence; target operation is carried out on each bit of data in the cached data of the pseudo-random binary sequence to obtain operation results, the operation results are accumulated to obtain an accumulation result, and the target operation comprises modulo operation and / or XOR operation; the accumulation result comprises the first number of accumulated values, the method does not need to depend on a local pseudo-random binary sequence, is high in independence, and can directly obtain the pseudo-random binary sequence seed by carrying out operation accumulation and judgment through the obtained cache data of the pseudo-random binary sequence; correlation operation is not needed, power consumption is low, the operation efficiency of the rapid recovery process of the pseudo-random binary sequence seeds can be improved, and therefore the detection capacity can be improved.

The embodiment of the invention provides a data processing method and device. The method comprises the steps that a first device determines a homomorphic encrypted ciphertext modulus; the ciphertext modulus is a prime number obtained by accumulation of n different multipliers of power and coefficient of 2, and n is an integer greater than or equal to 2 and less than or equal to 5; and performing homomorphic processing based on the ciphertext modulus, wherein the homomorphic processing can comprise at least one of homomorphic encryption, homomorphic decryption and homomorphic calculation. Generally, homomorphic encryption, homomorphic decryption, homomorphic calculation and other operations involve modulo operation or modulo operation, and the embodiment of the invention designs a modulus, so that the modulo operation or modulo operation can be more convenient and higher in efficiency. Therefore, the processing efficiency of homomorphic encryption, homomorphic decryption, homomorphic calculation and the like including modulo operation / modulo operation can be improved.

The present invention discloses a multi-level security information integrity authentication method based on active quantum walks, comprising the following steps: step 1: initialization of a keyed quantum hash function; step 2: execution of a controlled alternating active quantum walk method; and step 3: use POVM to measure and obtain the terminal quantum state |Ψ>. final Corresponding to the probability distribution P of each vertex on the ring; Step 4: Execute the post-processing method, process the probability of each vertex on the ring by interception and modulo operation, and connect to obtain the final hash value h. The present invention introduces the activity coefficient as a new parameter to participate in the construction of the keyed quantum hash function, and constructs a multi-level security information integrity authentication method based on active quantum walks. In terms of security, starting from the periodicity of quantum walks, the conditions for constructing a theoretically collision-resistant keyed quantum hash function are given; in terms of practicality, the flexibility and scalability of the keyed quantum hash function are improved, providing a practical solution for the practical application of the keyed quantum hash function.

A parallel multiplier for the Saber algorithm comprises a coefficient memory, two parallel pre-adding circuits, three parallel multiplication circuits and a post-adding circuit. The coefficient memory, the two parallel pre-adding circuits, the three parallel multiplication circuits and the post-adding circuit adopt a divide-and-conquer strategy, the two parallel pre-adding circuits perform parallel computation, and the three parallel multiplication circuits perform parallel computation, such that the computation time of modulo multiplication is shorted; the modulo operation of non-prime numbers is realized by limiting the bit width, such that the constraint that the modulus is a prime number is avoided; and the Karatsuba algorithm is called once, such that extra circuit area expenditure is reduced. Thus, the parallel multiplier for the Saber algorithm is implemented by hardware, low in computation complexity, not limited by the constraint that the modulus is a prime number, and low in circuit area expenditure.

The invention relates to the technical field of informatization management, and discloses a continuous education informatization management system based on a cloud platform, a honeycomb unit topology is constructed, each honeycomb unit is adjacent to six units, course identifiers are mapped to G course groups through a Hash algorithm and modulo operation, and each course group is divided into G groups; dividing request moments according to a sliding time window and a time slice width to generate a time slice identifier, and distributing a course selection request to a unique honeycomb unit; and adaptively adjusting the processing capacity of the honeycomb unit based on the historical request mean value, the standard deviation and the preset lower limit, controlling the request processing rhythm through a token bucket mechanism, and transferring the overflow request to an adjacent unit according to a polling mode when the queue exceeds a preset threshold value. And after the flood peak processing is finished, updating the historical request parameters according to the processing data to optimize the subsequent capacity configuration. The problems of space-time traffic imbalance and low resource allocation efficiency of a traditional system are solved, and space-time decentralized processing, dynamic load balancing and high-concurrency stability improvement of course selection requests are achieved.

An electronic system includes system memory having N interleaved channels, where N is not a power of two. A hardware-implemented method for the electronic system includes receiving a request to access the system memory, the request including an M-bit address; and processing the address to calculate a modulo N of the address without performing division-by-N. The modulo N of the address is calculated as [Σi αi mod N*2b<sub2>i < / sub2>mod N]mod N, where Σi αi*2b<sub2>i < / sub2>represents the M-bit address, ai is an ith word in the address, and 2b<sub2>i < / sub2>is a power of two associated with the ith word. The method further includes using the modulo N of the address as an offset to determine which of the N interleaved channels to access.

The invention relates to the technical field of data processing, in particular to a method, a device and equipment for replacing and desensitizing Chinese name fields. The method comprises the following steps: randomly arranging common Chinese characters of names to form a one-to-many mapping basic mapping table which comprises an original Chinese character set and at least one mapping Chinese character set; calculating the hash value of a real name to be desensitized, and then performing modulo operation to obtain the offset of each Chinese character; and matching each Chinese character in the real name in the original Chinese character set to obtain the corresponding desensitized Chinese character to combine into a final desensitized name. According to the embodiment of the invention, the relevance of the Chinese name field is ensured to the greatest extent, and the data analysis and mining application after desensitization is not influenced. Meanwhile, it is guaranteed that the algorithm is irreversible and high in safety, and data leakage in a larger range cannot be caused under the condition that the mapping relation between part of real data and desensitized data is leaked.

The present application provides a sequence seed recovery method, a computing device, a storage medium, and a product. The sequence seed recovery method comprises: acquiring cached data of a pseudo-random binary sequence; performing a target operation on each bit of data in the cached data of the pseudo-random binary sequence to obtain an operation result, and accumulating the operation results to obtain an accumulated result, wherein the target operation comprises a modulo operation and / or an exclusive OR operation; and performing decision on the basis of the accumulated result to obtain a pseudo-random binary sequence seed, wherein the accumulated result comprises a first number of accumulated values.

This disclosure relates to methods and systems for selecting secure prime numbers for a finite field Diffie-Hellman key exchange. A method for Diffie-Hellman key exchange includes: selecting a field size p in the format p = hq + 1, where q is a prime number of 1 plus factorial b such that q = (b! + 1), and h is a cofactor of a prime number such that p = hq + 1; selecting a generator integer g whose order modulo p is a prime number q or divisible by q; selecting a private key x; and calculating the public key g by applying arithmetic modulo operations on the prime field size p using the power of the private key x raised to the power of the generator g. x mod p; Sends the public key g to the communicating party. x mod p; Receive the second public key B from the communicating party. The second public key B includes the second private key y raised to the power of g, in the form g y The second private key y is chosen by the communicating party; and the key B is created from the received second public key B by applying arithmetic modulo operation on the size p of the prime field, by raising the second public key B to the power of the private key x. x .

Embodiments of the present application disclose a data processing method, a password service module, a chip, and an electronic device. The password service module receives a password service request instruction. The password service request instruction includes a password to be processed and a modulus to be processed. When the bit length of the password to be processed is less than or equal to a first length, an odd modulus is determined according to the modulus to be processed, and the password to be processed is subjected to a modulo operation using the odd modulus to obtain a first quotient and a first modulus. Wherein, the modulus to be processed is an even number; the odd modulus is equal to the modulus to be processed plus 1. A modulo result is determined according to the first quotient and the first modulus. Wherein, the modulo result represents the result of taking the modulo of the password to be processed using the modulus to be processed. When the bit length of the password to be processed is greater than the first length, the password to be processed is split into a first integer and a second integer. A first arithmetic process is performed based on the first integer, the second integer, and the odd modulus to obtain a modulo result.

A method for performing encoding on the basis of a parity check matrix of a low density parity check code according to the present embodiment comprises the steps of: generating a parity check matrix by a terminal, wherein the parity check matrix corresponds to a characteristic matrix, each component of the characteristic matrix corresponds to a shift index value determined through a modulo operation between a corresponding component in a basic matrix and Zc, which is a lifting value, and the basic matrix is a 42 x 52 matrix; and performing encoding of input data, by the terminal, using the parity check matrix, wherein the lifting value is associated with the length of the input data.

The present invention provides a convolution acceleration method and a convolution hardware accelerator, and relates to the field of hardware design. The convolution hardware accelerator includes a forward conversion module, an FNT module, a matrix dot multiplication module, an IFNT module, and an inverse conversion module. Based on the linear convolution property of the Fermat number transform, the convolution hardware accelerator is used to implement a forward Fermat number transform on two conversion matrices, and then perform dot multiplication on the result, and then perform an inverse Fermat number transform, thereby utilizing hardware resources to achieve convolution acceleration. Moreover, when the convolution hardware accelerator implements convolution acceleration, bit splitting, inversion, and bit splicing operations are used to replace the multiplication and modulo operations in the prior art during the forward Fermat number transform process and the inverse Fermat number transform process, thereby accelerating the convolution speed and effectively reducing the complexity of hardware implementation and the consumption of hardware resources.

The present application relates to a password generation method, apparatus, computer device, and storage medium. The method includes: obtaining a plurality of user identification data; for each of the user identification data, selecting random numerical values corresponding to each digit of the user identification data from a pre-generated random number queue; performing a modulo operation on the user identification data and the random numerical values corresponding to each digit of the user identification data to obtain user identification processing data corresponding to each of the user identification data; performing an encryption process on each of the user identification processing data to obtain a user identification encrypted data group; and generating a password according to each user identification encrypted data in the user identification encrypted data group. This method uses the user identification data as the data source of the password data and associates the user identification data with random numbers, which can improve the security of the generated password.