Optimization design method based on FPGA finite field multipier

Abstract

This invention discloses a optimum design method for the finite field multiplier on the base of FPGA. This invention defines those logic functions which can be realized with a single 4-LUT into 7 styles, and it will follow some steps to realize the optimization for the finite field multiplier. Firstly, it figures out the matrix form of the finite field multiplier according to the generator polynomial and initialize the integration of middle variables. Secondly, it will repeatedly search for the common logic functions in the elements in the Matrix Z, bringing in a new middle variable, and it will use this new middle variable to represent the output variable of those logic functions, modifying the Matrix Z. Finally, it will find out preferred logic functions that can be realized by a single 4-LUT. Then those logic functions will be decomposed into a series of logic functions that can be realized by a single 4-LUT, and Matrix Z and the integration of middle variables will be modified. After all above, we finally get a optimized finite field multiplier on the base of FPGA. The advantages are short key route and time delay.

Description

Technical field [0001] The invention belongs to electronic components in the field of communication and information processing applications, and relates to the use of field programmable gate arrays (FPGA) to realize the automated design of finite field multipliers, and specifically is an optimized design method of finite field multipliers based on FPGA. Background technique [0002] Using field programmable gate array (FPGA) to effectively implement finite field multipliers is an important technology that requires fast and flexible finite field multipliers. This technology is widely used in computer, communication, information security and other fields. It is software Radio, dynamic encryption and other core technologies in many IT fields. Finite field arithmetic is the basis of error control, such as BCH codes, Reed-Solomon codes, etc., and cryptography, such as ECC, DES, AES, etc. The speed of the finite field multiplier determines the implementation speed of algorithms in thes...

AI Technical Summary

Problems solved by technology

[0005] The purpose of the invention is to overcome the shortcoming that the existing finite field multiplier design method can not effectively utilize FPGA chip resources, provide a kind of basic structure characteristic based on 4-LUT FPGA, can realize the optimal design method of finite field multiplier, to shorten the limited The critical path of the domain multiplier, increasing the frequency of operation

Images