RS decoder low in hardware complexity

A technology of complexity and decoder, applied in the field of communication channel coding and decoding, which can solve the problems of consuming large hardware resources and computing speed, and cannot meet the requirements of low cost or high speed.

Active Publication Date: 2014-12-17
SUN YAT SEN UNIV +1
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Problems solved by technology

Due to the inverse operation of finite fields in the BM algorithm and the division operation of polynomials in the Euclid algorithm, these two operations will consume a lot of hardware resources and the op

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  • RS decoder low in hardware complexity
  • RS decoder low in hardware complexity
  • RS decoder low in hardware complexity

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Embodiment Construction

[0084] The specific embodiment of the present invention is further described below in conjunction with accompanying drawing:

[0085] The structural block diagram of the RS decoder of the low hardware complexity described in the present invention is as figure 2 As shown, it includes a synchronous FIFO, an adjoint polynomial calculation / money search multifunctional module, an error position polynomial / error estimation polynomial calculation module, a Forney algorithm module and a codeword error correction module. Among them, the adjoint polynomial calculation / money search multifunctional module uses the same hardware to complete the calculation of adjoint polynomial coefficients and the function of money search through time-division multiplexing, which significantly saves hardware resources; In the value polynomial calculation module, the inversion operation is eliminated when the DiBM algorithm is used to iteratively solve the error position polynomial. Compared with the iBM ...

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Abstract

The invention discloses an RS decoder low in hardware complexity. Received code words are stored; syndrome polynomial coefficient of the code words is calculated by utilizing Horner rules and used for time division to realize a chien searching function, and an error position is determined; polynomial coefficient of the error position is iteratively calculated according to the syndrome polynomial coefficient through a decomposed non-inversion Berlekamp-Massey algorithm, and polynomial calculation of an error estimated value is realized according to syndrome polynomial and error position polynomial time division; an error value on the error position is calculated; corresponding code words in a synchronous FIFO are corrected according to the error position and the error value. According to an iBM algorithm in the form of decomposition, inversion operation is eliminated during iterative solving of error position polynomial, and iteration is performed through decomposition, so that number of finite field multipliers is reduced, hardware complexity is lowered, hardware resources are saved to a great extent, and area and power consumption of a decoder chip is reduced.

Description

technical field [0001] The present invention relates to the technical field of communication channel coding and decoding, and more specifically, relates to an RS decoder with low hardware complexity. Background technique [0002] RS code is a kind of non-binary BCH (Bose Chaudhuri Hocquenghem) code with strong error correction ability, which was constructed by Reed (Reed) and Solomon (Solomon) in 1960 using MS (Mattson-Solomon) polynomial from. RS code can effectively correct random symbol errors and random burst errors, and is one of the most common channel coding schemes, and is widely used in various communication and data storage systems for error control. [0003] The RS code is based on the finite field GF(2 m ), that is, each symbol in the RS code is GF(2 m ) elements, the operations between the symbols are carried out according to the finite field algorithm. Generally, RS(n,n-2t) is used to represent an RS code, n represents the number of coded symbols, n-2t repr...

Claims

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Application Information

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IPC IPC(8): H03M13/15
Inventor 谭洪舟黄聪钟志铖赵钦耀曾龙辉其他发明人请求不公开姓名
Owner SUN YAT SEN UNIV
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