Implementation method of finite field multiplying unit with functions of detecting, correcting and locating error

An error localization, finite field technology, applied in data representation error detection/correction, error correction/detection using linear code, error correction/detection using block code, etc., can solve the problem of low error coverage and no error location module , can not deal with hardware and other problems, to achieve the effect of high data processing rate

Inactive Publication Date: 2011-05-25
BEIHANG UNIV
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Problems solved by technology

Finite field operations are widely used in the field of cryptography and coding. Among all finite field operations, finite field multiplication is the most important and complex. Currently, finite field multipliers at home and abroad generally have the following problems: 1. Mainly use parity Error detection is performed by means of verification, and even-numbered bit errors will be ignored, resulting in a slightly lower error coverage; 2. There is no error location module, so that when the finite field multiplier receives a fault attack, it cannot perform the first-time processing hardware question

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  • Implementation method of finite field multiplying unit with functions of detecting, correcting and locating error
  • Implementation method of finite field multiplying unit with functions of detecting, correcting and locating error
  • Implementation method of finite field multiplying unit with functions of detecting, correcting and locating error

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Embodiment Construction

[0034] In the present invention, the mathematical expression is described as follows:

[0035] Represents a finite field GF(2 with generator polynomial P(x) m an element of );

[0036] Represents a finite field GF(2 with generator polynomial P(x) m another element in );

[0037] C(x) means A(x) and B(x) in the finite field GF(2 m ) in the product;

[0038] P(x) represents the generator polynomial of the finite field, p i is the coefficient component of P(x);

[0039] mod P(x) represents the remainder of the polynomial divided by P(x);

[0040] g(x) represents a coding polynomial whose degree of (n, m) is n-m in the linear code;

[0041] x represents any indeterminate element;

[0042] x i Represents the element of degree i in the polynomial base;

[0043] m represents the dimension of the finite field under the polynomial basis;

[0044] a i Indicates that A(x) is in the polynomial basis x i coefficient;

[0045] b i Indicates that B(x) is under the polyno...

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Abstract

The invention provides an implementation method of a finite field multiplying unit with functions of detecting, correcting and locating an error. The finite field multiplying unit comprises an error locating unit, an error correction unit based on a redundant base, a finite field multiplication unit and an error detecting unit based on norm; and the finite field multiplying unit has the functions of detecting, correcting and locating the error. The finite field multiplying unit generated by the method has the function of locating the error so as to be convenient for dealing with hardware failure, and has the function of error correction so as to effectively resist the failure attack of an opponent.

Description

technical field [0001] The invention relates to a finite field multiplier, in particular to a realization method of a finite field multiplier system based on a systolic array with functions of error detection, error correction and error location. The multiplier implementation method is suitable for FPGA (Field Programmable Gate Array) and chip, and is the basis for block cipher to realize reconfigurable function. Background technique [0002] With the rapid development of computer technology and communication technology, people pay more and more attention to the issue of information security, and various new encryption techniques and attack techniques are constantly emerging. The glitch attack is very effective as a side-channel attack in the analysis of symmetric and asymmetric cryptographic algorithms. Therefore, eliminating errors in the calculation process becomes particularly important in preventing side-channel attacks. One of the simplest and most feasible methods t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/72H03M13/13
Inventor 郑志明邱望洁王文华张筱高莹王钊李洪革唐绍婷
Owner BEIHANG UNIV
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