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Parallel implementing method for determinant block interleaving device

A technology of packet interleaving and implementation method, applied in the field of communication, can solve the problems of fixed parallelism, impracticality, and a large number of register resources, and achieve the effect of improving the data processing rate

Inactive Publication Date: 2012-03-21
BEIJING INSTITUTE OF TECHNOLOGYGY
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Problems solved by technology

[0005] The disadvantage of the above invention is that it is only applicable when the values ​​of d and n are small. When d and n are large, the invention requires a large amount of register resources, so it is not practical; in addition, the degree of parallelism of the invention is fixed and cannot be implemented according to actual needs. flexible change

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  • Parallel implementing method for determinant block interleaving device
  • Parallel implementing method for determinant block interleaving device
  • Parallel implementing method for determinant block interleaving device

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example

[0068] Assume: interleaving depth d=6, interleaving width n=12, parallelism p=4, according to the formula n=w×p, then w=3.

[0069] Let a frame of 72 bits of data be x 0 , x 1 ,...,x 71 .

[0070] Take i equal to 0, 1, 2, 3 respectively, calculate the Indx values ​​according to formula (1) to be (0, 6, 12, 18) respectively, and calculate the Shuf values ​​according to formula (2) to be (0, 2, 1 , 3).

[0071] For 4-bit data (x 0 , x 1 , x 2 , x 3 ), the serial number k is equal to 0, and the SR value is calculated according to formula (3) to be 0. Therefore, the 4-bit data after sequence exchange and 0 times of cyclic shift to the right is (x 0 , x 2 , x 1 , x 3 ), the sequence exchange and right-shift cyclic shift diagram of this 4-bit data is as follows Figure 8 shown in .

[0072] Another example for 4-bit data (x 36 , x 37 , x 38 , x 39 ), the sequence number k is equal to 9, and the SR value is calculated according to formula (3) to be 3, therefore, the ...

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Abstract

The invention relates to a parallel accomplishing method for row type grouped interweaver, belonging to communication field. Interweaving depth is d, breadth is n for row type grouped interweaver; random factor of n is selected as parallelism degree p, n=w*p, w is positive integer. First sequence exchanger exchanges inputted p bit data in order, then executes ROR, then writes p bit data gotten from sequential exchange and ROR in p double port RAMs (random access memory) according to p address created by writing address creator; after writing a frame of data, then parallel reading p bit data from p double port RAMs according to read address created by read address creator, then executes ROL to get interweaved data. The invention can agilely selects parallelism degree p to accomplish parallel row type grouped interweaver, so promotes data processing rate p times to satisfy needs of high speed data transmission.

Description

technical field [0001] The invention relates to the technical field of communication, in particular to a parallel implementation method of a determinant packet interleaver. Background technique [0002] Determinant block interleaving is the most intuitive and simplest interleaving method in the interleaver. Its basic principle is to fill the input bit data into d×n matrix units row by row, such as figure 1 As shown in ; when all the matrix cells are filled, read out the contents of the matrix cells column by column, such as figure 2 shown in . Among them, d and n are two parameters of the determinant block interleaver, called interleaving depth and interleaving width respectively. In terms of interleaving function, the function of the determinant packet interleaver is to scramble the input bit data order and then re-output. The determinant packet interleaver takes the bit data with a frame length of d×n as the interleaving unit, Data undergoes the same interleaving opera...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L1/00H04L12/56
Inventor 范光荣匡镜明王华武楠杨德伟
Owner BEIJING INSTITUTE OF TECHNOLOGYGY
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