Key equation solving circuit of read-solomon decoder

Abstract

This invention discloses a Read-Solomon decoder key equation solution circuit. The aim is to avoid the long key path between the present registers, and the low working frequency of internal part of decoders. It includes R(x) shift register, Q(x) shift register, lambda(x) shift register, mu(x) shift register, the finite extent multiplier, the finite extent adder, the coefficient latch a0, b0 and a1. The characteristics are: it also includes the pipeline register C and E, the input end of the pipeline register C connects the finite extent adder A, the output end of the pipeline register C respectively connects the coefficient latch a1 and the finite extent multiplier C, the input end of the pipeline register E connects the finite extent adder C, the output end of the pipeline register E connects the finite extent multiplier G. Because increasing the number of the pipeline registers, the key path are shortened from '2XTmult+2XTadd' to 'Tmult+Tadd'. The highest working frequency of internal clock is 204.79MHz, and increases 63.6% of the present 133.33MHz.

Description

technical field [0001] The invention relates to a circuit for solving key equations of a Reed-Solomon decoder. Background technique [0002] Reed-Solomon codes (hereinafter referred to as RS codes) have strong error correction capability, can correct both random errors and burst errors, and are widely used in communication systems and storage systems. Whether the calculation amount of the decoding algorithm is small, whether the algorithm structure is regular, whether the decoding error rate is low, whether the decoder is simple and fast, whether it is convenient for hardware implementation, etc. are important indicators in the selection of RS codewords and hardware implementation. When decoding the RS code, the most important step is to solve the key equation to obtain the error value polynomial and the error position polynomial, which occupies the most resources and the largest amount of calculation. [0003] refer to figure 2 . In May 2000, Young-Jin Lim and Moon-ho Le...

AI Technical Summary

Problems solved by technology

According to the characteristics of the algorithm, this structure merges the iterations according to the odd and even times, the number of operation units is reduced, and the resources occupied are reduced, but its disadvantage is that there are two finite-field multipliers and two finite-field adders between the registers, and the critical path Too long, which limits the improvement of the internal clock operating frequency of the decoder circuit

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